pescx_cfg_wr      203 arch/mips/pci/pcie-octeon.c 		union cvmx_pescx_cfg_wr pescx_cfg_wr;
pescx_cfg_wr      204 arch/mips/pci/pcie-octeon.c 		pescx_cfg_wr.u64 = 0;
pescx_cfg_wr      205 arch/mips/pci/pcie-octeon.c 		pescx_cfg_wr.s.addr = cfg_offset;
pescx_cfg_wr      206 arch/mips/pci/pcie-octeon.c 		pescx_cfg_wr.s.data = val;
pescx_cfg_wr      207 arch/mips/pci/pcie-octeon.c 		cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);