pescx_cfg_rd      175 arch/mips/pci/pcie-octeon.c 		union cvmx_pescx_cfg_rd pescx_cfg_rd;
pescx_cfg_rd      176 arch/mips/pci/pcie-octeon.c 		pescx_cfg_rd.u64 = 0;
pescx_cfg_rd      177 arch/mips/pci/pcie-octeon.c 		pescx_cfg_rd.s.addr = cfg_offset;
pescx_cfg_rd      178 arch/mips/pci/pcie-octeon.c 		cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
pescx_cfg_rd      179 arch/mips/pci/pcie-octeon.c 		pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
pescx_cfg_rd      180 arch/mips/pci/pcie-octeon.c 		return pescx_cfg_rd.s.data;