per_ctx 129 drivers/gpu/drm/i915/gt/intel_engine_types.h } indirect_ctx, per_ctx; per_ctx 2253 drivers/gpu/drm/i915/gt/intel_lrc.c &wa_ctx->per_ctx }; per_ctx 3247 drivers/gpu/drm/i915/gt/intel_lrc.c if (wa_ctx->per_ctx.size) { per_ctx 3251 drivers/gpu/drm/i915/gt/intel_lrc.c (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; per_ctx 2988 drivers/gpu/drm/i915/gvt/cmd_parser.c if (!wa_ctx->per_ctx.valid) per_ctx 2992 drivers/gpu/drm/i915/gvt/cmd_parser.c per_ctx_start[1] = wa_ctx->per_ctx.guest_gma; per_ctx 540 drivers/gpu/drm/i915/gvt/scheduler.c (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma; per_ctx 568 drivers/gpu/drm/i915/gvt/scheduler.c wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1); per_ctx 1485 drivers/gpu/drm/i915/gvt/scheduler.c u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; per_ctx 1554 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4); per_ctx 1575 drivers/gpu/drm/i915/gvt/scheduler.c workload->wa_ctx.per_ctx.guest_gma = per_ctx 1576 drivers/gpu/drm/i915/gvt/scheduler.c per_ctx & PER_CTX_ADDR_MASK; per_ctx 1577 drivers/gpu/drm/i915/gvt/scheduler.c workload->wa_ctx.per_ctx.valid = per_ctx & 1; per_ctx 1578 drivers/gpu/drm/i915/gvt/scheduler.c if (workload->wa_ctx.per_ctx.valid) { per_ctx 1580 drivers/gpu/drm/i915/gvt/scheduler.c workload->wa_ctx.per_ctx.guest_gma, per_ctx 1583 drivers/gpu/drm/i915/gvt/scheduler.c workload->wa_ctx.per_ctx.guest_gma); per_ctx 76 drivers/gpu/drm/i915/gvt/scheduler.h struct shadow_per_ctx per_ctx;