pending_flush_mask 76 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask, pending_flush_mask 83 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask, pending_flush_mask 90 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, pending_flush_mask 92 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c ctx->pending_flush_mask = 0x0; pending_flush_mask 99 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c ctx->pending_flush_mask); pending_flush_mask 100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c ctx->pending_flush_mask |= flushbits; pending_flush_mask 105 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c return ctx->pending_flush_mask; pending_flush_mask 110 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask, pending_flush_mask 112 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); pending_flush_mask 173 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h u32 pending_flush_mask;