PRESCALE_GRPH_CONTROL 2109 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); PRESCALE_GRPH_CONTROL 2150 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); PRESCALE_GRPH_CONTROL 146 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_UPDATE(PRESCALE_GRPH_CONTROL, PRESCALE_GRPH_CONTROL 162 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_UPDATE(PRESCALE_GRPH_CONTROL, PRESCALE_GRPH_CONTROL 215 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); PRESCALE_GRPH_CONTROL 44 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(PRESCALE_GRPH_CONTROL, DCP, id), \ PRESCALE_GRPH_CONTROL 87 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \ PRESCALE_GRPH_CONTROL 208 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t PRESCALE_GRPH_CONTROL; PRESCALE_GRPH_CONTROL 497 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_UPDATE_4(PRESCALE_GRPH_CONTROL, PRESCALE_GRPH_CONTROL 44 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(PRESCALE_GRPH_CONTROL, DCP, id),\ PRESCALE_GRPH_CONTROL 95 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h uint32_t PRESCALE_GRPH_CONTROL; PRESCALE_GRPH_CONTROL 153 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\ PRESCALE_GRPH_CONTROL 154 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\ PRESCALE_GRPH_CONTROL 155 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ PRESCALE_GRPH_CONTROL 156 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\