pee               201 arch/mips/include/asm/octeon/cvmx-pci-defs.h 		uint32_t pee:1;
pee               215 arch/mips/include/asm/octeon/cvmx-pci-defs.h 		uint32_t pee:1;
pee               481 arch/mips/pci/pci-octeon.c 	cfg01.s.pee = 1;	/* PERR# Enable */