pdpu              139 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu, *tmp;
pdpu              149 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu = to_dpu_plane(plane);
pdpu              151 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
pdpu              153 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
pdpu              157 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pdpu->base.base.id, tmp->base.base.id,
pdpu              185 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			plane->base.id, pdpu->pipe - SSPP_VIG0,
pdpu              225 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              230 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pdpu->is_rt_pipe) {
pdpu              237 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				drm_rect_width(&pdpu->pipe_cfg.src_rect));
pdpu              246 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
pdpu              248 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_qos_cfg.creq_lut = qos_lut;
pdpu              250 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
pdpu              252 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
pdpu              256 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe - SSPP_VIG0,
pdpu              258 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->is_rt_pipe, total_fl, qos_lut);
pdpu              260 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
pdpu              271 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              275 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pdpu->is_rt_pipe) {
pdpu              276 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		danger_lut = pdpu->catalog->perf.danger_lut_tbl
pdpu              278 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		safe_lut = pdpu->catalog->perf.safe_lut_tbl
pdpu              286 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			danger_lut = pdpu->catalog->perf.danger_lut_tbl
pdpu              288 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			safe_lut = pdpu->catalog->perf.safe_lut_tbl
pdpu              291 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			danger_lut = pdpu->catalog->perf.danger_lut_tbl
pdpu              293 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			safe_lut = pdpu->catalog->perf.safe_lut_tbl
pdpu              298 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_qos_cfg.danger_lut = danger_lut;
pdpu              299 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_qos_cfg.safe_lut = safe_lut;
pdpu              301 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
pdpu              304 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_qos_cfg.danger_lut,
pdpu              305 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_qos_cfg.safe_lut);
pdpu              309 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe - SSPP_VIG0,
pdpu              312 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.danger_lut,
pdpu              313 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.safe_lut);
pdpu              315 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
pdpu              316 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			&pdpu->pipe_qos_cfg);
pdpu              328 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              331 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
pdpu              332 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.danger_vblank =
pdpu              333 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pdpu->pipe_sblk->danger_vblank;
pdpu              334 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.vblank_en = enable;
pdpu              339 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.vblank_en = false;
pdpu              340 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
pdpu              344 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.danger_safe_en = enable;
pdpu              346 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pdpu->is_rt_pipe) {
pdpu              347 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.vblank_en = false;
pdpu              348 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.danger_safe_en = false;
pdpu              353 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe - SSPP_VIG0,
pdpu              354 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.danger_safe_en,
pdpu              355 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.vblank_en,
pdpu              356 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.creq_vblank,
pdpu              357 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_qos_cfg.danger_vblank,
pdpu              358 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->is_rt_pipe);
pdpu              360 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
pdpu              361 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			&pdpu->pipe_qos_cfg);
pdpu              372 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              377 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
pdpu              378 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
pdpu              379 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
pdpu              380 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
pdpu              381 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ot_params.is_wfd = !pdpu->is_rt_pipe;
pdpu              384 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
pdpu              396 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              402 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
pdpu              403 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
pdpu              404 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
pdpu              405 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	qos_params.is_rt = pdpu->is_rt_pipe;
pdpu              421 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              422 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
pdpu              428 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
pdpu              430 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
pdpu              431 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
pdpu              432 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
pdpu              435 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
pdpu              440 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
pdpu              501 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
pdpu              532 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pdpu) {
pdpu              537 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
pdpu              538 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
pdpu              540 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
pdpu              542 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
pdpu              543 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->csc_ptr->csc_mv[0],
pdpu              544 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->csc_ptr->csc_mv[1],
pdpu              545 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->csc_ptr->csc_mv[2]);
pdpu              548 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
pdpu              556 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	_dpu_plane_setup_scaler3(pdpu, pstate,
pdpu              557 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			drm_rect_width(&pdpu->pipe_cfg.src_rect),
pdpu              558 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			drm_rect_height(&pdpu->pipe_cfg.src_rect),
pdpu              559 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			drm_rect_width(&pdpu->pipe_cfg.dst_rect),
pdpu              560 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			drm_rect_height(&pdpu->pipe_cfg.dst_rect),
pdpu              572 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
pdpu              576 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	const struct drm_plane *plane = &pdpu->base;
pdpu              579 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "\n");
pdpu              588 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
pdpu              589 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
pdpu              594 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_cfg.src_rect.x1 = 0;
pdpu              595 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_cfg.src_rect.y1 = 0;
pdpu              596 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_cfg.src_rect.x2 =
pdpu              597 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			drm_rect_width(&pdpu->pipe_cfg.dst_rect);
pdpu              598 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_cfg.src_rect.y2 =
pdpu              599 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			drm_rect_height(&pdpu->pipe_cfg.dst_rect);
pdpu              600 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
pdpu              602 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (pdpu->pipe_hw->ops.setup_format)
pdpu              603 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
pdpu              607 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (pdpu->pipe_hw->ops.setup_rects)
pdpu              608 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
pdpu              609 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					&pdpu->pipe_cfg,
pdpu              612 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (pdpu->pipe_hw->ops.setup_pe)
pdpu              613 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
pdpu              616 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (pdpu->pipe_hw->ops.setup_scaler &&
pdpu              618 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
pdpu              619 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					&pdpu->pipe_cfg, &pstate->pixel_ext,
pdpu              766 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              769 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
pdpu              775 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
pdpu              800 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
pdpu              810 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              818 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
pdpu              846 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              856 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);
pdpu              858 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					  pdpu->pipe_sblk->maxupscale << 16,
pdpu              861 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
pdpu              877 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
pdpu              884 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		(!(pdpu->features & DPU_SSPP_SCALER) ||
pdpu              885 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		 !(pdpu->features & (BIT(DPU_SSPP_CSC)
pdpu              887 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu,
pdpu              893 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
pdpu              902 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
pdpu              908 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
pdpu              914 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
pdpu              924 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu;
pdpu              932 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu = to_dpu_plane(plane);
pdpu              939 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->is_error)
pdpu              941 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		_dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
pdpu              942 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
pdpu              944 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
pdpu              945 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc)
pdpu              946 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
pdpu              959 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu;
pdpu              964 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu = to_dpu_plane(plane);
pdpu              965 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->is_error = error;
pdpu              971 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu              979 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
pdpu              981 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	_dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
pdpu              985 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
pdpu              988 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
pdpu              993 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_cfg.src_rect = state->src;
pdpu              996 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_cfg.src_rect.x1 >>= 16;
pdpu              997 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_cfg.src_rect.x2 >>= 16;
pdpu              998 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_cfg.src_rect.y1 >>= 16;
pdpu              999 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_cfg.src_rect.y2 >>= 16;
pdpu             1001 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_cfg.dst_rect = state->dst;
pdpu             1003 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
pdpu             1006 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
pdpu             1011 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->pipe_hw->ops.setup_rects) {
pdpu             1012 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
pdpu             1013 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pdpu->pipe_cfg,
pdpu             1017 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->pipe_hw->ops.setup_pe &&
pdpu             1019 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
pdpu             1027 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->pipe_hw->ops.setup_scaler &&
pdpu             1029 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
pdpu             1030 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pdpu->pipe_cfg, &pstate->pixel_ext,
pdpu             1033 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->pipe_hw->ops.setup_multirect)
pdpu             1034 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_multirect(
pdpu             1035 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pdpu->pipe_hw,
pdpu             1039 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->pipe_hw->ops.setup_format) {
pdpu             1056 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
pdpu             1059 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (pdpu->pipe_hw->ops.setup_cdp) {
pdpu             1064 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
pdpu             1073 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
pdpu             1078 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			_dpu_plane_setup_csc(pdpu);
pdpu             1080 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->csc_ptr = 0;
pdpu             1096 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu             1106 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect)
pdpu             1107 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw,
pdpu             1114 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu             1117 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->is_error = false;
pdpu             1119 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "\n");
pdpu             1130 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu;
pdpu             1137 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu = to_dpu_plane(plane);
pdpu             1139 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "\n");
pdpu             1147 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
pdpu             1149 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "\n");
pdpu             1151 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu) {
pdpu             1154 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		mutex_destroy(&pdpu->lock);
pdpu             1159 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		dpu_hw_sspp_destroy(pdpu->pipe_hw);
pdpu             1161 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		kfree(pdpu);
pdpu             1175 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu;
pdpu             1188 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu = to_dpu_plane(plane);
pdpu             1191 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
pdpu             1195 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "\n");
pdpu             1206 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu;
pdpu             1214 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu = to_dpu_plane(plane);
pdpu             1215 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG_PLANE(pdpu, "\n");
pdpu             1225 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
pdpu             1237 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu             1240 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pdpu->is_rt_pipe)
pdpu             1317 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu             1319 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
pdpu             1323 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->debugfs_root =
pdpu             1324 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		debugfs_create_dir(pdpu->pipe_name,
pdpu             1329 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->debugfs_root, &pdpu->features);
pdpu             1332 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
pdpu             1337 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->debugfs_root, &pdpu->debugfs_src);
pdpu             1341 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
pdpu             1346 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pdpu->debugfs_root,
pdpu             1347 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pdpu->debugfs_scaler);
pdpu             1350 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pdpu->debugfs_root,
pdpu             1351 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pdpu->debugfs_default_scale);
pdpu             1356 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
pdpu             1361 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pdpu->debugfs_root, &pdpu->debugfs_csc);
pdpu             1366 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->debugfs_root,
pdpu             1370 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->debugfs_root,
pdpu             1374 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->debugfs_root,
pdpu             1378 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->debugfs_root,
pdpu             1383 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->debugfs_root,
pdpu             1402 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu = to_dpu_plane(plane);
pdpu             1404 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	debugfs_remove_recursive(pdpu->debugfs_root);
pdpu             1460 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane *pdpu;
pdpu             1468 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
pdpu             1469 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pdpu) {
pdpu             1476 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	plane = &pdpu->base;
pdpu             1477 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe = pipe;
pdpu             1478 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->is_virtual = (master_plane_id != 0);
pdpu             1479 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	INIT_LIST_HEAD(&pdpu->mplane_list);
pdpu             1484 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list);
pdpu             1488 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog,
pdpu             1490 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (IS_ERR(pdpu->pipe_hw)) {
pdpu             1492 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		ret = PTR_ERR(pdpu->pipe_hw);
pdpu             1494 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	} else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
pdpu             1500 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->features = pdpu->pipe_hw->cap->features;
pdpu             1501 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
pdpu             1502 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pdpu->pipe_sblk) {
pdpu             1507 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu->is_virtual) {
pdpu             1508 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		format_list = pdpu->pipe_sblk->virt_format_list;
pdpu             1509 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		num_formats = pdpu->pipe_sblk->virt_num_formats;
pdpu             1512 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		format_list = pdpu->pipe_sblk->format_list;
pdpu             1513 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		num_formats = pdpu->pipe_sblk->num_formats;
pdpu             1522 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pdpu->catalog = kms->catalog;
pdpu             1548 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
pdpu             1550 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	mutex_init(&pdpu->lock);
pdpu             1552 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name,
pdpu             1557 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pdpu && pdpu->pipe_hw)
pdpu             1558 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		dpu_hw_sspp_destroy(pdpu->pipe_hw);
pdpu             1560 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	kfree(pdpu);
pdpu              432 drivers/mmc/host/sdhci-tegra.c 					       u16 pdpu)
pdpu              438 drivers/mmc/host/sdhci-tegra.c 	reg |= pdpu;
pdpu              520 drivers/mmc/host/sdhci-tegra.c 	u16 pdpu;
pdpu              526 drivers/mmc/host/sdhci-tegra.c 		pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
pdpu              529 drivers/mmc/host/sdhci-tegra.c 		pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
pdpu              533 drivers/mmc/host/sdhci-tegra.c 			pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
pdpu              535 drivers/mmc/host/sdhci-tegra.c 			pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
pdpu              539 drivers/mmc/host/sdhci-tegra.c 	tegra_sdhci_set_pad_autocal_offset(host, pdpu);