pcw_chg_addr       46 drivers/clk/mediatek/clk-pll.c 	void __iomem	*pcw_chg_addr;
pcw_chg_addr      139 drivers/clk/mediatek/clk-pll.c 	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
pcw_chg_addr      140 drivers/clk/mediatek/clk-pll.c 	writel(chg, pll->pcw_chg_addr);
pcw_chg_addr      317 drivers/clk/mediatek/clk-pll.c 		pll->pcw_chg_addr = base + data->pcw_chg_reg;
pcw_chg_addr      319 drivers/clk/mediatek/clk-pll.c 		pll->pcw_chg_addr = pll->base_addr + REG_CON1;