pcw 63 drivers/clk/mediatek/clk-pll.c u32 pcw, int postdiv) pcw 76 drivers/clk/mediatek/clk-pll.c vco = (u64)fin * pcw; pcw 115 drivers/clk/mediatek/clk-pll.c static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, pcw 137 drivers/clk/mediatek/clk-pll.c val |= pcw << pll->data->pcw_shift; pcw 159 drivers/clk/mediatek/clk-pll.c static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, pcw 193 drivers/clk/mediatek/clk-pll.c *pcw = (u32)_pcw; pcw 200 drivers/clk/mediatek/clk-pll.c u32 pcw = 0; pcw 203 drivers/clk/mediatek/clk-pll.c mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); pcw 204 drivers/clk/mediatek/clk-pll.c mtk_pll_set_rate_regs(pll, pcw, postdiv); pcw 214 drivers/clk/mediatek/clk-pll.c u32 pcw; pcw 219 drivers/clk/mediatek/clk-pll.c pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; pcw 220 drivers/clk/mediatek/clk-pll.c pcw &= GENMASK(pll->data->pcwbits - 1, 0); pcw 222 drivers/clk/mediatek/clk-pll.c return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); pcw 229 drivers/clk/mediatek/clk-pll.c u32 pcw = 0; pcw 232 drivers/clk/mediatek/clk-pll.c mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); pcw 234 drivers/clk/mediatek/clk-pll.c return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); pcw 168 drivers/gpu/drm/mediatek/mtk_mipi_tx.c u64 pcw; pcw 233 drivers/gpu/drm/mediatek/mtk_mipi_tx.c pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, pcw 235 drivers/gpu/drm/mediatek/mtk_mipi_tx.c writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);