pcsx_int_en_reg   122 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c 	union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
pcsx_int_en_reg   143 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c 	pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
pcsx_int_en_reg   232 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
pcsx_int_en_reg   275 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
pcsx_int_en_reg   278 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	pcsx_int_en_reg.u64 = 0;
pcsx_int_en_reg   281 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.algnlos_en = 1;
pcsx_int_en_reg   282 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.synlos_en = 1;
pcsx_int_en_reg   283 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.bitlckls_en = 1;
pcsx_int_en_reg   284 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.rxsynbad_en = 1;
pcsx_int_en_reg   285 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.rxbad_en = 1;
pcsx_int_en_reg   286 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.txflt_en = 1;
pcsx_int_en_reg   290 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.algnlos_en = 1;
pcsx_int_en_reg   291 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.synlos_en = 1;
pcsx_int_en_reg   292 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.bitlckls_en = 0;	/* Happens if XAUI module is not installed */
pcsx_int_en_reg   293 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.rxsynbad_en = 1;
pcsx_int_en_reg   294 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.rxbad_en = 1;
pcsx_int_en_reg   295 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcsx_int_en_reg.s.txflt_en = 1;
pcsx_int_en_reg   297 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);