pcs_int_en_reg    234 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	union cvmx_pcsx_intx_en_reg pcs_int_en_reg;
pcs_int_en_reg    237 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	pcs_int_en_reg.u64 = 0;
pcs_int_en_reg    241 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.sync_bad_en = 1;
pcs_int_en_reg    242 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.an_bad_en = 1;
pcs_int_en_reg    243 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.rxlock_en = 1;
pcs_int_en_reg    244 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.rxbad_en = 1;
pcs_int_en_reg    246 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.txbad_en = 1;
pcs_int_en_reg    247 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.txfifo_en = 1;
pcs_int_en_reg    248 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.txfifu_en = 1;
pcs_int_en_reg    249 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.an_err_en = 1;
pcs_int_en_reg    256 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.sync_bad_en = 1;
pcs_int_en_reg    257 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.an_bad_en = 1;
pcs_int_en_reg    258 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.rxlock_en = 1;
pcs_int_en_reg    259 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.rxbad_en = 1;
pcs_int_en_reg    261 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.txbad_en = 1;
pcs_int_en_reg    262 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.txfifo_en = 1;
pcs_int_en_reg    263 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.txfifu_en = 1;
pcs_int_en_reg    264 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 		pcs_int_en_reg.s.an_err_en = 1;
pcs_int_en_reg    268 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c 	cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);