pciercx_cfg032    387 arch/mips/pci/pcie-octeon.c 	union cvmx_pciercx_cfg032 pciercx_cfg032;
pciercx_cfg032    495 arch/mips/pci/pcie-octeon.c 	pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
pciercx_cfg032    496 arch/mips/pci/pcie-octeon.c 	pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
pciercx_cfg032    497 arch/mips/pci/pcie-octeon.c 	cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
pciercx_cfg032    589 arch/mips/pci/pcie-octeon.c 	union cvmx_pciercx_cfg032 pciercx_cfg032;
pciercx_cfg032    641 arch/mips/pci/pcie-octeon.c 		pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
pciercx_cfg032    642 arch/mips/pci/pcie-octeon.c 	} while (pciercx_cfg032.s.dlla == 0);
pciercx_cfg032    656 arch/mips/pci/pcie-octeon.c 	switch (pciercx_cfg032.s.nlw) {
pciercx_cfg032    704 arch/mips/pci/pcie-octeon.c 	union cvmx_pciercx_cfg032 pciercx_cfg032;
pciercx_cfg032   1074 arch/mips/pci/pcie-octeon.c 	pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
pciercx_cfg032   1075 arch/mips/pci/pcie-octeon.c 	cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
pciercx_cfg032   1093 arch/mips/pci/pcie-octeon.c 	union cvmx_pciercx_cfg032 pciercx_cfg032;
pciercx_cfg032   1107 arch/mips/pci/pcie-octeon.c 		pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
pciercx_cfg032   1108 arch/mips/pci/pcie-octeon.c 	} while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
pciercx_cfg032   1119 arch/mips/pci/pcie-octeon.c 	switch (pciercx_cfg032.s.nlw) {
pciercx_cfg032   1156 arch/mips/pci/pcie-octeon.c 	union cvmx_pciercx_cfg032 pciercx_cfg032;
pciercx_cfg032   1429 arch/mips/pci/pcie-octeon.c 	pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
pciercx_cfg032   1430 arch/mips/pci/pcie-octeon.c 	pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);