pciebase          291 arch/mips/pci/pci-xlp.c 	uint64_t pciebase;
pciebase          308 arch/mips/pci/pci-xlp.c 			pciebase = nlm_get_pcie_base(n, link);
pciebase          309 arch/mips/pci/pci-xlp.c 			if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
pciebase          315 arch/mips/pci/pci-xlp.c 			reg = nlm_read_pci_reg(pciebase, 0xf);
pciebase          318 arch/mips/pci/pci-xlp.c 			nlm_write_pci_reg(pciebase, 0xf, reg);
pciebase         1679 drivers/crypto/inside-secure/safexcel.c 	void __iomem *pciebase;
pciebase         1720 drivers/crypto/inside-secure/safexcel.c 		pciebase = pcim_iomap_table(pdev)[2];
pciebase         1721 drivers/crypto/inside-secure/safexcel.c 		val = readl(pciebase + EIP197_XLX_IRQ_BLOCK_ID_ADDR);
pciebase         1728 drivers/crypto/inside-secure/safexcel.c 			       pciebase + EIP197_XLX_USER_VECT_LUT0_ADDR);
pciebase         1730 drivers/crypto/inside-secure/safexcel.c 			       pciebase + EIP197_XLX_USER_VECT_LUT1_ADDR);
pciebase         1732 drivers/crypto/inside-secure/safexcel.c 			       pciebase + EIP197_XLX_USER_VECT_LUT2_ADDR);
pciebase         1734 drivers/crypto/inside-secure/safexcel.c 			       pciebase + EIP197_XLX_USER_VECT_LUT3_ADDR);
pciebase         1738 drivers/crypto/inside-secure/safexcel.c 			       pciebase + EIP197_XLX_USER_INT_ENB_MSK);