pcie_speed_table  554 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
pcie_speed_table  565 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
pcie_speed_table  571 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.pcie_speed_table.count = max_entry - 1;
pcie_speed_table  575 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
pcie_speed_table  580 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
pcie_speed_table  585 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
pcie_speed_table  590 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
pcie_speed_table  595 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
pcie_speed_table  600 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
pcie_speed_table  606 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.pcie_speed_table.count = 6;
pcie_speed_table  610 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
pcie_speed_table  611 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
pcie_speed_table  616 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
pcie_speed_table  617 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->dpm_table.pcie_speed_table.count,
pcie_speed_table 2795 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	*pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
pcie_speed_table 3662 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
pcie_speed_table 3663 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					dpm_table->pcie_speed_table.dpm_levels
pcie_speed_table 3664 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					[dpm_table->pcie_speed_table.count - 1].value :
pcie_speed_table 3665 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					dpm_table->pcie_speed_table.dpm_levels[i].value);
pcie_speed_table 3868 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
pcie_speed_table 4447 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
pcie_speed_table  106 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	struct smu7_single_dpm_table  pcie_speed_table;
pcie_speed_table 1003 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
pcie_speed_table 1005 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
pcie_speed_table 1007 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
pcie_speed_table 1014 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		(uint8_t)dpm_table->pcie_speed_table.count;
pcie_speed_table 1016 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
pcie_speed_table 2052 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
pcie_speed_table 2056 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
pcie_speed_table  838 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
pcie_speed_table  840 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
pcie_speed_table  842 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				dpm_table->pcie_speed_table.dpm_levels[i].param1);
pcie_speed_table  850 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(uint8_t)dpm_table->pcie_speed_table.count;
pcie_speed_table  852 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
pcie_speed_table 1012 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
pcie_speed_table  772 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
pcie_speed_table  774 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
pcie_speed_table  776 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
pcie_speed_table  788 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		(uint8_t)dpm_table->pcie_speed_table.count;
pcie_speed_table  790 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
pcie_speed_table  776 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
pcie_speed_table  778 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
pcie_speed_table  780 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				dpm_table->pcie_speed_table.dpm_levels[i].param1);
pcie_speed_table  788 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(uint8_t)dpm_table->pcie_speed_table.count;
pcie_speed_table  792 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
pcie_speed_table  985 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
pcie_speed_table 1988 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
pcie_speed_table  515 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
pcie_speed_table  517 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
pcie_speed_table  519 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
pcie_speed_table  531 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		(uint8_t)dpm_table->pcie_speed_table.count;
pcie_speed_table  533 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
pcie_speed_table  693 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
pcie_speed_table 2346 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
pcie_speed_table 2350 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
pcie_speed_table  578 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
pcie_speed_table  580 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
pcie_speed_table  582 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				dpm_table->pcie_speed_table.dpm_levels[i].param1);
pcie_speed_table  590 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(uint8_t)dpm_table->pcie_speed_table.count;
pcie_speed_table  594 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
pcie_speed_table  869 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
pcie_speed_table 2040 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
pcie_speed_table 2044 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			hw_data->dpm_table.pcie_speed_table.count;
pcie_speed_table 2109 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
pcie_speed_table 2633 drivers/gpu/drm/radeon/ci_dpm.c 	for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
pcie_speed_table 2635 drivers/gpu/drm/radeon/ci_dpm.c 			(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
pcie_speed_table 2637 drivers/gpu/drm/radeon/ci_dpm.c 			r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
pcie_speed_table 2643 drivers/gpu/drm/radeon/ci_dpm.c 	pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
pcie_speed_table 2645 drivers/gpu/drm/radeon/ci_dpm.c 		ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
pcie_speed_table 3409 drivers/gpu/drm/radeon/ci_dpm.c 				  &pi->dpm_table.pcie_speed_table,
pcie_speed_table 3413 drivers/gpu/drm/radeon/ci_dpm.c 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
pcie_speed_table 3417 drivers/gpu/drm/radeon/ci_dpm.c 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
pcie_speed_table 3420 drivers/gpu/drm/radeon/ci_dpm.c 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
pcie_speed_table 3423 drivers/gpu/drm/radeon/ci_dpm.c 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
pcie_speed_table 3426 drivers/gpu/drm/radeon/ci_dpm.c 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
pcie_speed_table 3429 drivers/gpu/drm/radeon/ci_dpm.c 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
pcie_speed_table 3432 drivers/gpu/drm/radeon/ci_dpm.c 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
pcie_speed_table 3436 drivers/gpu/drm/radeon/ci_dpm.c 	pi->dpm_table.pcie_speed_table.count = 6;
pcie_speed_table 3666 drivers/gpu/drm/radeon/ci_dpm.c 	table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
pcie_speed_table 3723 drivers/gpu/drm/radeon/ci_dpm.c 	struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
pcie_speed_table 4189 drivers/gpu/drm/radeon/ci_dpm.c 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
pcie_speed_table   71 drivers/gpu/drm/radeon/ci_dpm.h 	struct ci_single_dpm_table pcie_speed_table;