pbn 29 arch/powerpc/mm/ptdump/bats.c phys_addr_t pbn = PHYS_BAT_ADDR(lower); pbn 41 arch/powerpc/mm/ptdump/bats.c seq_printf(m, "0x%016llx ", pbn); pbn 43 arch/powerpc/mm/ptdump/bats.c seq_printf(m, "0x%08x ", pbn); pbn 255 drivers/bluetooth/hci_ag6xx.c struct pbn_entry *pbn = (void *)fw_ptr; pbn 258 drivers/bluetooth/hci_ag6xx.c if (pbn->addr == 0xffffffff) { pbn 264 drivers/bluetooth/hci_ag6xx.c addr = le32_to_cpu(pbn->addr); pbn 265 drivers/bluetooth/hci_ag6xx.c plen = le32_to_cpu(pbn->plen); pbn 267 drivers/bluetooth/hci_ag6xx.c if (fw->data + fw->size <= pbn->data + plen) { pbn 275 drivers/bluetooth/hci_ag6xx.c err = intel_mem_write(hdev, addr, plen, pbn->data); pbn 281 drivers/bluetooth/hci_ag6xx.c fw_ptr = pbn->data + plen; pbn 192 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c int pbn = 0; pbn 238 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c pbn = drm_dp_calc_pbn_mode(clock, bpp); pbn 240 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); pbn 241 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots); pbn 2522 drivers/gpu/drm/amd/display/dc/core/dc_link.c struct fixed31_32 pbn; pbn 2583 drivers/gpu/drm/amd/display/dc/core/dc_link.c pbn = get_pbn_from_timing(pipe_ctx); pbn 2584 drivers/gpu/drm/amd/display/dc/core/dc_link.c avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); pbn 284 drivers/gpu/drm/drm_dp_mst_topology.c buf[idx] = (req->u.allocate_payload.pbn >> 8); pbn 286 drivers/gpu/drm/drm_dp_mst_topology.c buf[idx] = (req->u.allocate_payload.pbn & 0xff); pbn 770 drivers/gpu/drm/drm_dp_mst_topology.c u8 vcpi, uint16_t pbn, pbn 779 drivers/gpu/drm/drm_dp_mst_topology.c req.u.allocate_payload.pbn = pbn; pbn 2245 drivers/gpu/drm/drm_dp_mst_topology.c int pbn) pbn 2276 drivers/gpu/drm/drm_dp_mst_topology.c pbn, port->num_sdp_streams, sinks); pbn 2356 drivers/gpu/drm/drm_dp_mst_topology.c ret = drm_dp_payload_send_msg(mgr, port, id, port->vcpi.pbn); pbn 3179 drivers/gpu/drm/drm_dp_mst_topology.c int pbn) pbn 3183 drivers/gpu/drm/drm_dp_mst_topology.c num_slots = DIV_ROUND_UP(pbn, mgr->pbn_div); pbn 3193 drivers/gpu/drm/drm_dp_mst_topology.c struct drm_dp_vcpi *vcpi, int pbn, int slots) pbn 3201 drivers/gpu/drm/drm_dp_mst_topology.c vcpi->pbn = pbn; pbn 3243 drivers/gpu/drm/drm_dp_mst_topology.c struct drm_dp_mst_port *port, int pbn) pbn 3276 drivers/gpu/drm/drm_dp_mst_topology.c req_slots = DIV_ROUND_UP(pbn, mgr->pbn_div); pbn 3367 drivers/gpu/drm/drm_dp_mst_topology.c struct drm_dp_mst_port *port, int pbn, int slots) pbn 3380 drivers/gpu/drm/drm_dp_mst_topology.c port->vcpi.vcpi, port->vcpi.pbn, pbn); pbn 3381 drivers/gpu/drm/drm_dp_mst_topology.c if (pbn == port->vcpi.pbn) { pbn 3387 drivers/gpu/drm/drm_dp_mst_topology.c ret = drm_dp_init_vcpi(mgr, &port->vcpi, pbn, slots); pbn 3390 drivers/gpu/drm/drm_dp_mst_topology.c DIV_ROUND_UP(pbn, mgr->pbn_div), ret); pbn 3394 drivers/gpu/drm/drm_dp_mst_topology.c pbn, port->vcpi.num_slots); pbn 3452 drivers/gpu/drm/drm_dp_mst_topology.c port->vcpi.pbn = 0; pbn 917 drivers/gpu/drm/i915/display/intel_display_types.h int pbn; pbn 63 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, pbn 67 drivers/gpu/drm/i915/display/intel_dp_mst.c port, crtc_state->pbn); pbn 323 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->pbn, pbn 122 drivers/gpu/drm/nouveau/dispnv50/atom.h int pbn; pbn 758 drivers/gpu/drm/nouveau/dispnv50/disp.c args.vcpi.pbn = mstc->port->vcpi.pbn; pbn 766 drivers/gpu/drm/nouveau/dispnv50/disp.c args.vcpi.pbn, args.vcpi.aligned_pbn); pbn 809 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3); pbn 813 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->dp.pbn); pbn 859 drivers/gpu/drm/nouveau/dispnv50/disp.c r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, pbn 96 drivers/gpu/drm/nouveau/include/nvif/cl5070.h __u16 pbn; pbn 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h u8 slot_nr, u16 pbn, u16 aligned); pbn 256 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c args->v0.num_slots, args->v0.pbn, pbn 263 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c args->v0.pbn, pbn 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c u8 slot, u8 slot_nr, u16 pbn, u16 aligned) pbn 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn); pbn 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c u8 slot, u8 slot_nr, u16 pbn, u16 aligned) pbn 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn); pbn 443 drivers/gpu/drm/radeon/radeon_dp_mst.c mst_enc->pbn); pbn 446 drivers/gpu/drm/radeon/radeon_dp_mst.c mst_enc->pbn, slots); pbn 455 drivers/gpu/drm/radeon/radeon_dp_mst.c fixed_pbn = drm_int2fixp(mst_enc->pbn); pbn 517 drivers/gpu/drm/radeon/radeon_dp_mst.c mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp); pbn 456 drivers/gpu/drm/radeon/radeon_mode.h int pbn; pbn 59 fs/nilfs2/gcinode.c sector_t pbn, __u64 vbn, pbn 72 fs/nilfs2/gcinode.c if (pbn == 0) { pbn 75 fs/nilfs2/gcinode.c err = nilfs_dat_translate(nilfs->ns_dat, vbn, &pbn); pbn 92 fs/nilfs2/gcinode.c bh->b_blocknr = pbn; pbn 126 fs/nilfs2/gcinode.c int nilfs_gccache_submit_read_node(struct inode *inode, sector_t pbn, pbn 132 fs/nilfs2/gcinode.c vbn ? : pbn, pbn, REQ_OP_READ, 0, pbn 133 fs/nilfs2/gcinode.c out_bh, &pbn); pbn 40 include/drm/drm_dp_mst_helper.h int pbn; pbn 253 include/drm/drm_dp_mst_helper.h u16 pbn; pbn 617 include/drm/drm_dp_mst_helper.h struct drm_dp_mst_port *port, int pbn, int slots); pbn 630 include/drm/drm_dp_mst_helper.h int pbn); pbn 662 include/drm/drm_dp_mst_helper.h struct drm_dp_mst_port *port, int pbn);