patched_crtc_timing 287 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struct dc_crtc_timing patched_crtc_timing; patched_crtc_timing 304 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c patched_crtc_timing = *dc_crtc_timing; patched_crtc_timing 306 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing); patched_crtc_timing 310 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.h_total = patched_crtc_timing.h_total; patched_crtc_timing 312 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c patched_crtc_timing.h_addressable; patched_crtc_timing 313 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.v_total = patched_crtc_timing.v_total; patched_crtc_timing 314 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.v_addressable = patched_crtc_timing.v_addressable; patched_crtc_timing 317 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.h_sync_width = patched_crtc_timing.h_sync_width; patched_crtc_timing 319 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.v_sync_width = patched_crtc_timing.v_sync_width; patched_crtc_timing 323 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c patched_crtc_timing.h_border_left; patched_crtc_timing 325 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c patched_crtc_timing.h_border_right; patched_crtc_timing 326 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.v_overscan_top = patched_crtc_timing.v_border_top; patched_crtc_timing 328 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c patched_crtc_timing.v_border_bottom; patched_crtc_timing 331 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY == 1) patched_crtc_timing 334 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY == 1) patched_crtc_timing 337 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (patched_crtc_timing.flags.INTERLACE == 1) patched_crtc_timing 340 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1) patched_crtc_timing 345 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c program_horz_count_by_2(tg, &patched_crtc_timing); patched_crtc_timing 347 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing); patched_crtc_timing 3078 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dc_crtc_timing patched_crtc_timing; patched_crtc_timing 3084 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c patched_crtc_timing = *dc_crtc_timing; patched_crtc_timing 3085 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c apply_front_porch_workaround(&patched_crtc_timing); patched_crtc_timing 3087 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1; patched_crtc_timing 3089 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c vesa_sync_start = patched_crtc_timing.v_addressable + patched_crtc_timing 3090 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c patched_crtc_timing.v_border_bottom + patched_crtc_timing 3091 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c patched_crtc_timing.v_front_porch; patched_crtc_timing 3093 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c asic_blank_end = (patched_crtc_timing.v_total - patched_crtc_timing 3095 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c patched_crtc_timing.v_border_top) patched_crtc_timing 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct dc_crtc_timing patched_crtc_timing; patched_crtc_timing 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing = *dc_crtc_timing; patched_crtc_timing 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c apply_front_porch_workaround(&patched_crtc_timing); patched_crtc_timing 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_H_TOTAL, patched_crtc_timing.h_total - 1); patched_crtc_timing 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); patched_crtc_timing 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c asic_blank_start = patched_crtc_timing.h_total - patched_crtc_timing 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.h_front_porch; patched_crtc_timing 186 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.h_border_right - patched_crtc_timing 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.h_addressable - patched_crtc_timing 188 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.h_border_left; patched_crtc_timing 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? patched_crtc_timing 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c v_total = patched_crtc_timing.v_total - 1; patched_crtc_timing 215 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c v_sync_end = patched_crtc_timing.v_sync_width; patched_crtc_timing 222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c asic_blank_start = patched_crtc_timing.v_total - patched_crtc_timing 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.v_front_porch; patched_crtc_timing 227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.v_border_bottom - patched_crtc_timing 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.v_addressable - patched_crtc_timing 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.v_border_top; patched_crtc_timing 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? patched_crtc_timing 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (patched_crtc_timing.flags.INTERLACE == 1) patched_crtc_timing 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (patched_crtc_timing.flags.INTERLACE == 1) patched_crtc_timing 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) patched_crtc_timing 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct dc_crtc_timing patched_crtc_timing; patched_crtc_timing 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing = *dc_crtc_timing; patched_crtc_timing 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c apply_front_porch_workaround(&patched_crtc_timing); patched_crtc_timing 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; patched_crtc_timing 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.v_border_bottom - patched_crtc_timing 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.v_addressable - patched_crtc_timing 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.v_border_top; patched_crtc_timing 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (patched_crtc_timing.flags.INTERLACE == 1) {