part2             671 drivers/gpu/drm/gma500/psb_intel_sdvo.c 		psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
part2             716 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	BUILD_BUG_ON(sizeof(dtd->part2) != 8);
part2             720 drivers/gpu/drm/gma500/psb_intel_sdvo.c 				     &dtd->part2, sizeof(dtd->part2));
part2             758 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.h_sync_off = h_sync_offset & 0xff;
part2             759 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.h_sync_width = h_sync_len & 0xff;
part2             760 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
part2             762 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
part2             766 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.dtd_flags = 0x18;
part2             768 drivers/gpu/drm/gma500/psb_intel_sdvo.c 		dtd->part2.dtd_flags |= 0x2;
part2             770 drivers/gpu/drm/gma500/psb_intel_sdvo.c 		dtd->part2.dtd_flags |= 0x4;
part2             772 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.sdvo_flags = 0;
part2             773 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
part2             774 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	dtd->part2.reserved = 0;
part2             782 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
part2             783 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
part2             784 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
part2             785 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
part2             792 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
part2             793 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
part2             794 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
part2             796 drivers/gpu/drm/gma500/psb_intel_sdvo.c 		(dtd->part2.v_sync_off_width & 0xf);
part2             797 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
part2             804 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	if (dtd->part2.dtd_flags & 0x2)
part2             806 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	if (dtd->part2.dtd_flags & 0x4)
part2            1097 drivers/gpu/drm/gma500/psb_intel_sdvo.c 	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
part2              91 drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h     } part2;
part2             750 drivers/gpu/drm/i915/display/intel_sdvo.c 		intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
part2             757 drivers/gpu/drm/i915/display/intel_sdvo.c 		intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
part2             814 drivers/gpu/drm/i915/display/intel_sdvo.c 	BUILD_BUG_ON(sizeof(dtd->part2) != 8);
part2             818 drivers/gpu/drm/i915/display/intel_sdvo.c 				     &dtd->part2, sizeof(dtd->part2));
part2             862 drivers/gpu/drm/i915/display/intel_sdvo.c 	dtd->part2.h_sync_off = h_sync_offset & 0xff;
part2             863 drivers/gpu/drm/i915/display/intel_sdvo.c 	dtd->part2.h_sync_width = h_sync_len & 0xff;
part2             864 drivers/gpu/drm/i915/display/intel_sdvo.c 	dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
part2             866 drivers/gpu/drm/i915/display/intel_sdvo.c 	dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
part2             870 drivers/gpu/drm/i915/display/intel_sdvo.c 	dtd->part2.dtd_flags = 0x18;
part2             872 drivers/gpu/drm/i915/display/intel_sdvo.c 		dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
part2             874 drivers/gpu/drm/i915/display/intel_sdvo.c 		dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
part2             876 drivers/gpu/drm/i915/display/intel_sdvo.c 		dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
part2             878 drivers/gpu/drm/i915/display/intel_sdvo.c 	dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
part2             888 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
part2             889 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
part2             890 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
part2             891 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
part2             898 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
part2             899 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
part2             900 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
part2             902 drivers/gpu/drm/i915/display/intel_sdvo.c 		(dtd->part2.v_sync_off_width & 0xf);
part2             903 drivers/gpu/drm/i915/display/intel_sdvo.c 	mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
part2             909 drivers/gpu/drm/i915/display/intel_sdvo.c 	if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
part2             911 drivers/gpu/drm/i915/display/intel_sdvo.c 	if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
part2             915 drivers/gpu/drm/i915/display/intel_sdvo.c 	if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
part2            1237 drivers/gpu/drm/i915/display/intel_sdvo.c 	intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
part2            1495 drivers/gpu/drm/i915/display/intel_sdvo.c 		input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
part2            1544 drivers/gpu/drm/i915/display/intel_sdvo.c 	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
part2            1621 drivers/gpu/drm/i915/display/intel_sdvo.c 		if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
part2            1626 drivers/gpu/drm/i915/display/intel_sdvo.c 		if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
part2             102 drivers/gpu/drm/i915/display/intel_sdvo_regs.h 	} part2;