parent1           198 drivers/clk/davinci/da8xx-cfgchip.c 	const char *parent1;
parent1           241 drivers/clk/davinci/da8xx-cfgchip.c 	const char * const parent_names[] = { info->parent0, info->parent1 };
parent1           271 drivers/clk/davinci/da8xx-cfgchip.c 	.parent1 = "div4.5",
parent1           293 drivers/clk/davinci/da8xx-cfgchip.c 	.parent1 = "pll1_sysclk2",
parent1           511 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	char clk_name[32], parent1[32], parent2[32], vco_name[32];
parent1           532 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
parent1           534 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 			parent1, CLK_SET_RATE_PARENT,
parent1           540 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
parent1           542 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 			parent1, CLK_SET_RATE_PARENT,
parent1           546 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
parent1           549 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 				parent1, 0, pll_28nm->mmio +
parent1           554 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
parent1           558 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 				parent1, parent2
parent1           563 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
parent1           566 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 				parent1, CLK_SET_RATE_PARENT, 1, 4);