pad_mii_tx         39 drivers/net/dsa/sja1105/sja1105.h 	u64 pad_mii_tx[SJA1105_NUM_PORTS];
pad_mii_tx        367 drivers/net/dsa/sja1105/sja1105_clocking.c 	struct sja1105_cfg_pad_mii_tx pad_mii_tx;
pad_mii_tx        371 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.d32_os    = 3; /* TXD[3:2] output stage: */
pad_mii_tx        373 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.d10_os    = 3; /* TXD[1:0] output stage: */
pad_mii_tx        375 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.d32_ipud  = 2; /* TXD[3:2] input stage: */
pad_mii_tx        377 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.d10_ipud  = 2; /* TXD[1:0] input stage: */
pad_mii_tx        379 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.ctrl_os   = 3; /* TX_CTL / TX_ER output stage */
pad_mii_tx        380 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */
pad_mii_tx        381 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.clk_os    = 3; /* TX_CLK output stage */
pad_mii_tx        382 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.clk_ih    = 0; /* TX_CLK input hysteresis (default) */
pad_mii_tx        383 drivers/net/dsa/sja1105/sja1105_clocking.c 	pad_mii_tx.clk_ipud  = 2; /* TX_CLK input stage (default) */
pad_mii_tx        384 drivers/net/dsa/sja1105/sja1105_clocking.c 	sja1105_cfg_pad_mii_tx_packing(packed_buf, &pad_mii_tx, PACK);
pad_mii_tx        387 drivers/net/dsa/sja1105/sja1105_clocking.c 					   regs->pad_mii_tx[port],
pad_mii_tx        504 drivers/net/dsa/sja1105/sja1105_spi.c 	.pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
pad_mii_tx        533 drivers/net/dsa/sja1105/sja1105_spi.c 	.pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},