p2pll 1087 drivers/gpu/drm/radeon/atombios_crtc.c pll = &rdev->clock.p2pll; p2pll 265 drivers/gpu/drm/radeon/radeon.h struct radeon_pll p2pll; p2pll 1146 drivers/gpu/drm/radeon/radeon_atombios.c struct radeon_pll *p2pll = &rdev->clock.p2pll; p2pll 1197 drivers/gpu/drm/radeon/radeon_atombios.c *p2pll = *p1pll; p2pll 109 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *p2pll = &rdev->clock.p2pll; p2pll 120 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_freq = p2pll->reference_freq = (*val) / 10; p2pll 124 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->reference_div = p1pll->reference_div; p2pll 132 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_min = 100; p2pll 133 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_max = 1350; p2pll 134 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_min = 20000; p2pll 135 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_max = 50000; p2pll 141 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_min = 40; p2pll 142 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_max = 500; p2pll 143 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_min = 12500; p2pll 144 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_max = 35000; p2pll 183 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *p2pll = &rdev->clock.p2pll; p2pll 210 drivers/gpu/drm/radeon/radeon_clocks.c if (p2pll->reference_div < 2) p2pll 211 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->reference_div = 12; p2pll 231 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->reference_freq = 1432; p2pll 236 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->reference_freq = 2700; p2pll 244 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->reference_div = p1pll->reference_div; p2pll 251 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_min = 100; p2pll 252 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_max = 1350; p2pll 253 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_min = 20000; p2pll 254 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_max = 50000; p2pll 260 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_min = 40; p2pll 261 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_in_max = 500; p2pll 262 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_min = 12500; p2pll 263 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->pll_out_max = 35000; p2pll 283 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->min_post_div = 2; p2pll 284 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->max_post_div = 0x7f; p2pll 285 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->min_frac_feedback_div = 0; p2pll 286 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->max_frac_feedback_div = 9; p2pll 292 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->min_post_div = 1; p2pll 293 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->max_post_div = 12; p2pll 294 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->min_frac_feedback_div = 0; p2pll 295 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->max_frac_feedback_div = 0; p2pll 315 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->min_ref_div = 2; p2pll 316 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->max_ref_div = 0x3ff; p2pll 317 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->min_feedback_div = 4; p2pll 318 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->max_feedback_div = 0x7ff; p2pll 319 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->best_vco = 0; p2pll 737 drivers/gpu/drm/radeon/radeon_combios.c struct radeon_pll *p2pll = &rdev->clock.p2pll; p2pll 762 drivers/gpu/drm/radeon/radeon_combios.c *p2pll = *p1pll; p2pll 774 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll = &rdev->clock.p2pll; p2pll 249 drivers/gpu/drm/radeon/radeon_legacy_tv.c pll = &rdev->clock.p2pll;