p1pll 1084 drivers/gpu/drm/radeon/atombios_crtc.c pll = &rdev->clock.p1pll; p1pll 264 drivers/gpu/drm/radeon/radeon.h struct radeon_pll p1pll; p1pll 1145 drivers/gpu/drm/radeon/radeon_atombios.c struct radeon_pll *p1pll = &rdev->clock.p1pll; p1pll 1158 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->reference_freq = p1pll 1160 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->reference_div = 0; p1pll 1163 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->pll_out_min = p1pll 1166 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->pll_out_min = p1pll 1168 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->pll_out_max = p1pll 1172 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->lcd_pll_out_min = p1pll 1174 drivers/gpu/drm/radeon/radeon_atombios.c if (p1pll->lcd_pll_out_min == 0) p1pll 1175 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->lcd_pll_out_min = p1pll->pll_out_min; p1pll 1176 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->lcd_pll_out_max = p1pll 1178 drivers/gpu/drm/radeon/radeon_atombios.c if (p1pll->lcd_pll_out_max == 0) p1pll 1179 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->lcd_pll_out_max = p1pll->pll_out_max; p1pll 1181 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->lcd_pll_out_min = p1pll->pll_out_min; p1pll 1182 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->lcd_pll_out_max = p1pll->pll_out_max; p1pll 1185 drivers/gpu/drm/radeon/radeon_atombios.c if (p1pll->pll_out_min == 0) { p1pll 1187 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->pll_out_min = 64800; p1pll 1189 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->pll_out_min = 20000; p1pll 1192 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->pll_in_min = p1pll 1194 drivers/gpu/drm/radeon/radeon_atombios.c p1pll->pll_in_max = p1pll 1197 drivers/gpu/drm/radeon/radeon_atombios.c *p2pll = *p1pll; p1pll 1279 drivers/gpu/drm/radeon/radeon_atombios.c *dcpll = *p1pll; p1pll 108 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *p1pll = &rdev->clock.p1pll; p1pll 120 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_freq = p2pll->reference_freq = (*val) / 10; p1pll 121 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; p1pll 122 drivers/gpu/drm/radeon/radeon_clocks.c if (p1pll->reference_div < 2) p1pll 123 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = 12; p1pll 124 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->reference_div = p1pll->reference_div; p1pll 128 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_min = 100; p1pll 129 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_max = 1350; p1pll 130 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_min = 20000; p1pll 131 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_max = 50000; p1pll 137 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_min = 40; p1pll 138 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_max = 500; p1pll 139 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_min = 12500; p1pll 140 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_max = 35000; p1pll 149 drivers/gpu/drm/radeon/radeon_clocks.c spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; p1pll 182 drivers/gpu/drm/radeon/radeon_clocks.c struct radeon_pll *p1pll = &rdev->clock.p1pll; p1pll 197 drivers/gpu/drm/radeon/radeon_clocks.c if (p1pll->reference_div < 2) { p1pll 201 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = p1pll 204 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; p1pll 205 drivers/gpu/drm/radeon/radeon_clocks.c if (p1pll->reference_div < 2) p1pll 206 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = 12; p1pll 208 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = 12; p1pll 230 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_freq = 1432; p1pll 235 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_freq = 2700; p1pll 240 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = p1pll 242 drivers/gpu/drm/radeon/radeon_clocks.c if (p1pll->reference_div < 2) p1pll 243 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->reference_div = 12; p1pll 244 drivers/gpu/drm/radeon/radeon_clocks.c p2pll->reference_div = p1pll->reference_div; p1pll 247 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_min = 100; p1pll 248 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_max = 1350; p1pll 249 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_min = 20000; p1pll 250 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_max = 50000; p1pll 256 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_min = 40; p1pll 257 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_in_max = 500; p1pll 258 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_min = 12500; p1pll 259 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->pll_out_max = 35000; p1pll 279 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->min_post_div = 2; p1pll 280 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->max_post_div = 0x7f; p1pll 281 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->min_frac_feedback_div = 0; p1pll 282 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->max_frac_feedback_div = 9; p1pll 288 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->min_post_div = 1; p1pll 289 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->max_post_div = 16; p1pll 290 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->min_frac_feedback_div = 0; p1pll 291 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->max_frac_feedback_div = 0; p1pll 309 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->min_ref_div = 2; p1pll 310 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->max_ref_div = 0x3ff; p1pll 311 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->min_feedback_div = 4; p1pll 312 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->max_feedback_div = 0x7ff; p1pll 313 drivers/gpu/drm/radeon/radeon_clocks.c p1pll->best_vco = 0; p1pll 736 drivers/gpu/drm/radeon/radeon_combios.c struct radeon_pll *p1pll = &rdev->clock.p1pll; p1pll 748 drivers/gpu/drm/radeon/radeon_combios.c p1pll->reference_freq = RBIOS16(pll_info + 0xe); p1pll 749 drivers/gpu/drm/radeon/radeon_combios.c p1pll->reference_div = RBIOS16(pll_info + 0x10); p1pll 750 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_out_min = RBIOS32(pll_info + 0x12); p1pll 751 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_out_max = RBIOS32(pll_info + 0x16); p1pll 752 drivers/gpu/drm/radeon/radeon_combios.c p1pll->lcd_pll_out_min = p1pll->pll_out_min; p1pll 753 drivers/gpu/drm/radeon/radeon_combios.c p1pll->lcd_pll_out_max = p1pll->pll_out_max; p1pll 756 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_in_min = RBIOS32(pll_info + 0x36); p1pll 757 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); p1pll 759 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_in_min = 40; p1pll 760 drivers/gpu/drm/radeon/radeon_combios.c p1pll->pll_in_max = 500; p1pll 762 drivers/gpu/drm/radeon/radeon_combios.c *p2pll = *p1pll; p1pll 776 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll = &rdev->clock.p1pll; p1pll 251 drivers/gpu/drm/radeon/radeon_legacy_tv.c pll = &rdev->clock.p1pll;