p15 290 arch/arm/include/asm/assembler.h mcr p15, 0, r0, c7, c5, 4 p15 306 arch/arm/include/asm/assembler.h ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb p15 54 arch/arm/include/asm/cp15.h "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 p15 56 arch/arm/include/asm/cp15.h "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64 p15 14 arch/arm/include/asm/tls.h mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register p15 15 arch/arm/include/asm/tls.h mcr p15, 0, \tp, c13, c0, 3 @ set TLS register p15 16 arch/arm/include/asm/tls.h mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register p15 26 arch/arm/include/asm/tls.h mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register p15 27 arch/arm/include/asm/tls.h mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register p15 28 arch/arm/include/asm/tls.h mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register p15 49 arch/arm/include/asm/uaccess-asm.h mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register p15 63 arch/arm/include/asm/uaccess-asm.h mcr p15, 0, \tmp, c3, c0, 0 p15 90 arch/arm/include/asm/uaccess-asm.h DACR( mrc p15, 0, \tmp0, c3, c0, 0) p15 96 arch/arm/include/asm/uaccess-asm.h mcr p15, 0, \tmp2, c3, c0, 0 p15 102 arch/arm/include/asm/uaccess-asm.h mcr p15, 0, \tmp2, c3, c0, 0 p15 112 arch/arm/include/asm/uaccess-asm.h DACR( mcr p15, 0, \tmp0, c3, c0, 0) p15 70 arch/arm/mach-tegra/sleep.h mrc p15, 0, \rd, c0, c0, 5 p15 82 arch/arm/mach-tegra/sleep.h mrc p15, 0, \tmp1, c0, c0, 0 p15 90 arch/arm/mach-tegra/sleep.h mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR p15 92 arch/arm/mach-tegra/sleep.h mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR p15 96 arch/arm/mach-tegra/sleep.h mrceq p15, 0, \tmp1, c0, c0, 5 p15 92 arch/ia64/kernel/minstate.h tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \ p15 63 samples/bpf/spintest_kern.c SEC("kprobe/htab_map_update_elem")PROG(p15)