ovly_ch 392 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u8 ovly_ch = 0; /* TODO: Only primary plane now */ ovly_ch 395 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_XY0(ovly_ch)); ovly_ch 396 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val); ovly_ch 397 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_XY1(ovly_ch)); ovly_ch 398 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val); ovly_ch 399 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_CTL(ovly_ch)); ovly_ch 400 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val); ovly_ch 667 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */ ovly_ch 681 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch)); ovly_ch 682 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch)); ovly_ch 688 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(val, base + ADE_OVLY_CH_CTL(ovly_ch)); ovly_ch 690 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), ovly_ch 696 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u8 ovly_ch = 0; /* TODO: Only primary plane now */ ovly_ch 699 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST, ovly_ch 702 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),