ovlp               19 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	int ovlp;
ovlp               87 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	flush |= ovlp2flush(mdp4_crtc->ovlp);
ovlp              181 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	int i, ovlp = mdp4_crtc->ovlp;
ovlp              184 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
ovlp              185 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
ovlp              186 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
ovlp              187 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
ovlp              211 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
ovlp              212 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
ovlp              213 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
ovlp              214 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
ovlp              215 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
ovlp              216 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
ovlp              217 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
ovlp              218 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
ovlp              229 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	int ovlp = mdp4_crtc->ovlp;
ovlp              251 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
ovlp              252 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
ovlp              255 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
ovlp              257 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
ovlp              632 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 	mdp4_crtc->ovlp = ovlp_id;
ovlp               72 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline uint32_t ovlp2flush(int ovlp)
ovlp               74 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h 	switch (ovlp) {