overflown 185 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c unsigned long overflown; overflown 189 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c overflown = readl(ddrc_pmu->base + DDRC_INT_STATUS); overflown 190 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c if (!overflown) overflown 197 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c for_each_set_bit(idx, &overflown, DDRC_NR_COUNTERS) { overflown 175 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c unsigned long overflown; overflown 179 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c overflown = readl(hha_pmu->base + HHA_INT_STATUS); overflown 180 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c if (!overflown) overflown 187 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c for_each_set_bit(idx, &overflown, HHA_NR_COUNTERS) { overflown 174 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c unsigned long overflown; overflown 178 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c overflown = readl(l3c_pmu->base + L3C_INT_STATUS); overflown 179 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c if (!overflown) overflown 186 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c for_each_set_bit(idx, &overflown, L3C_NR_COUNTERS) {