out_format        449 drivers/gpu/drm/amd/display/dc/dc_types.h 	enum dwb_scaler_mode		out_format;	/* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
out_format        256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format,
out_format        259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	if (params->out_format != dwb_scaler_mode_bypass444) {
out_format        273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 		enum dwb_scaler_mode out_format,
out_format        291 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	dump_info->format	= out_format;
out_format        528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	enum dwb_scaler_mode out_format,
out_format       1859 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
out_format       2223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
out_format         95 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h 		enum dwb_scaler_mode out_format,
out_format        628 drivers/media/platform/exynos4-is/fimc-is-param.h 	u32 out_format;