otg_inst          428 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 	int otg_inst;
otg_inst          239 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		     int otg_inst)
otg_inst          245 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (otg_inst == -1) {
otg_inst          253 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		if (amdgpu_crtc->otg_inst == otg_inst)
otg_inst         3752 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
otg_inst         3781 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
otg_inst         4822 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	acrtc->otg_inst = -1;
otg_inst         5358 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	acrtc->otg_inst = -1;
otg_inst         6278 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				acrtc->otg_inst = status->primary_otg_inst;
otg_inst          634 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 	if (acrtc->otg_inst == -1)
otg_inst          637 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 	irq_source = dal_irq_type + acrtc->otg_inst;
otg_inst         1207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
otg_inst         1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
otg_inst          728 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
otg_inst         1030 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
otg_inst         1034 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
otg_inst          328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
otg_inst         1941 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
otg_inst          323 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned char otg_inst;
otg_inst          568 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 		OTGInstPlane[mode_lib->vba.NumberOfActivePlanes] = dst->otg_inst;
otg_inst          135 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h 	void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);