ot_lim             63 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 		u32 *ot_lim, struct dpu_vbif_set_ot_params *params)
ot_lim             85 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 			*ot_lim = tbl->cfg[i].ot_limit;
ot_lim             93 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 			pps, *ot_lim);
ot_lim            105 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	u32 ot_lim = 0;
ot_lim            114 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 		ot_lim = vbif->cap->default_ot_wr_limit;
ot_lim            116 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 		ot_lim = vbif->cap->default_ot_rd_limit;
ot_lim            122 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	if (ot_lim == 0)
ot_lim            126 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	_dpu_vbif_apply_dynamic_ot_limit(vbif, &ot_lim, params);
ot_lim            131 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 		if (val == ot_lim)
ot_lim            132 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 			ot_lim = 0;
ot_lim            137 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 			vbif->idx - VBIF_0, params->xin_id, ot_lim);
ot_lim            138 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	return ot_lim;
ot_lim            154 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	u32 ot_lim;
ot_lim            184 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	ot_lim = _dpu_vbif_get_ot_limit(vbif, params) & 0xFF;
ot_lim            186 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	if (ot_lim == 0)
ot_lim            189 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	trace_dpu_perf_set_ot(params->num, params->xin_id, ot_lim,
ot_lim            194 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 	vbif->ops.set_limit_conf(vbif, params->xin_id, params->rd, ot_lim);