optc1 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->tg_regs->reg optc1 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->base.ctx optc1 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->tg_shift->field_name, optc1->tg_mask->field_name optc1 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vready_offset = vready_offset; optc1 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vstartup_start = vstartup_start; optc1 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vupdate_offset = vupdate_offset; optc1 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vupdate_width = vupdate_width; optc1 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (optc1->vstartup_start == 0) { optc1 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c VSTARTUP_START, optc1->vstartup_start); optc1 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c VUPDATE_OFFSET, optc1->vupdate_offset, optc1 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c VUPDATE_WIDTH, optc1->vupdate_width); optc1 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c VREADY_OFFSET, optc1->vready_offset); optc1 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->signal = signal; optc1 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vready_offset = vready_offset; optc1 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vstartup_start = vstartup_start; optc1 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vupdate_offset = vupdate_offset; optc1 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->vupdate_width = vupdate_width; optc1 242 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || optc1 243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || optc1 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->signal == SIGNAL_TYPE_EDP) { optc1 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) optc1 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; optc1 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if ((optc1->vstartup_start/2)*2 > asic_blank_end) optc1 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 448 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 496 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->h_total > optc1->max_h_total || optc1 540 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->v_total > optc1->max_v_total) optc1 544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (h_blank < optc1->min_h_blank) optc1 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (timing->h_sync_width < optc1->min_h_sync_width || optc1 548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c timing->v_sync_width < optc1->min_v_sync_width) optc1 551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; optc1 576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 587 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 648 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 662 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 712 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 755 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 789 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 806 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 824 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 847 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 904 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void optc1_read_otg_state(struct optc *optc1, optc1 1350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1374 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 1520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c void dcn10_timing_generator_init(struct optc *optc1) optc1 1522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->base.funcs = &dcn10_tg_funcs; optc1 1524 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; optc1 1525 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; optc1 1527 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->min_h_blank = 32; optc1 1528 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->min_v_blank = 3; optc1 1529 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->min_v_blank_interlace = 5; optc1 1530 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->min_h_sync_width = 8; optc1 1531 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->min_v_sync_width = 1; optc1 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h void optc1_read_otg_state(struct optc *optc1, optc1 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->tg_regs->reg optc1 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->base.ctx optc1 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->tg_shift->field_name, optc1->tg_mask->field_name optc1 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->opp_count = 1; optc1 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->opp_count = opp_cnt; optc1 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c struct optc *optc1 = DCN10TG_FROM_TG(optc); optc1 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void dcn20_timing_generator_init(struct optc *optc1) optc1 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->base.funcs = &dcn20_tg_funcs; optc1 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; optc1 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; optc1 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->min_h_blank = 32; optc1 482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->min_v_blank = 3; optc1 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->min_v_blank_interlace = 5; optc1 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. optc1 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->min_v_sync_width = 1;