opps 113 arch/arm/mach-vexpress/spc.c struct ve_spc_opp *opps[MAX_CLUSTERS]; opps 260 arch/arm/mach-vexpress/spc.c struct ve_spc_opp *opps = info->opps[cluster]; opps 270 arch/arm/mach-vexpress/spc.c opps += perf; opps 271 arch/arm/mach-vexpress/spc.c *freq = opps->freq; opps 280 arch/arm/mach-vexpress/spc.c struct ve_spc_opp *opps = info->opps[cluster]; opps 284 arch/arm/mach-vexpress/spc.c for (idx = 0; idx < max_opp; idx++, opps++) { opps 285 arch/arm/mach-vexpress/spc.c ftmp = opps->freq; opps 303 arch/arm/mach-vexpress/spc.c struct ve_spc_opp *opps = info->opps[cluster]; opps 305 arch/arm/mach-vexpress/spc.c for (idx = 0; idx < max_opp; idx++, opps++) opps 306 arch/arm/mach-vexpress/spc.c if (opps->freq == freq) opps 404 arch/arm/mach-vexpress/spc.c struct ve_spc_opp *opps; opps 406 arch/arm/mach-vexpress/spc.c opps = kcalloc(MAX_OPPS, sizeof(*opps), GFP_KERNEL); opps 407 arch/arm/mach-vexpress/spc.c if (!opps) opps 410 arch/arm/mach-vexpress/spc.c info->opps[cluster] = opps; opps 413 arch/arm/mach-vexpress/spc.c for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) { opps 416 arch/arm/mach-vexpress/spc.c opps->freq = (data & FREQ_MASK) * MULT_FACTOR; opps 417 arch/arm/mach-vexpress/spc.c opps->u_volt = (data >> VOLT_SHIFT) * 1000; opps 431 arch/arm/mach-vexpress/spc.c struct ve_spc_opp *opps; opps 437 arch/arm/mach-vexpress/spc.c opps = info->opps[cluster]; opps 439 arch/arm/mach-vexpress/spc.c for (idx = 0; idx < max_opp; idx++, opps++) { opps 440 arch/arm/mach-vexpress/spc.c ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt); opps 443 arch/arm/mach-vexpress/spc.c opps->freq, opps->u_volt); opps 67 drivers/clk/clk-scpi.c const struct scpi_opp *opp = clk->info->opps; opps 92 drivers/clk/clk-scpi.c opp = clk->info->opps + idx; opps 107 drivers/clk/clk-scpi.c const struct scpi_opp *opp = clk->info->opps; opps 307 drivers/firmware/arm_scpi.c } opps[MAX_DVFS_OPPS]; opps 635 drivers/firmware/arm_scpi.c info->opps = kcalloc(info->count, sizeof(*opp), GFP_KERNEL); opps 636 drivers/firmware/arm_scpi.c if (!info->opps) { opps 641 drivers/firmware/arm_scpi.c for (i = 0, opp = info->opps; i < info->count; i++, opp++) { opps 642 drivers/firmware/arm_scpi.c opp->freq = le32_to_cpu(buf.opps[i].freq); opps 643 drivers/firmware/arm_scpi.c opp->m_volt = le32_to_cpu(buf.opps[i].m_volt); opps 646 drivers/firmware/arm_scpi.c sort(info->opps, info->count, sizeof(*opp), opp_cmp_func, NULL); opps 692 drivers/firmware/arm_scpi.c if (!info->opps) opps 695 drivers/firmware/arm_scpi.c for (opp = info->opps, idx = 0; idx < info->count; idx++, opp++) { opps 869 drivers/firmware/arm_scpi.c kfree(info->dvfs[i]->opps); opps 1218 drivers/gpu/drm/amd/display/dc/core/dc_resource.c split_pipe->stream_res.opp = pool->opps[i]; opps 1622 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.opp = pool->opps[i]; opps 1892 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.opp = pool->opps[tg_inst]; opps 687 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.opps[i] != NULL) opps 688 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce110_opp_destroy(&pool->base.opps[i]); opps 1036 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.opps[i] = dce100_opp_create(ctx, i); opps 1037 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.opps[i] == NULL) { opps 744 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.opps[i] != NULL) opps 745 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_opp_destroy(&pool->base.opps[i]); opps 1065 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; opps 1192 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->opps[pool->pipe_count] = &dce110_oppv->base; opps 1394 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.opps[i] = dce110_opp_create(ctx, i); opps 1395 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.opps[i] == NULL) { opps 706 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.opps[i] != NULL) opps 707 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce110_opp_destroy(&pool->base.opps[i]); opps 1281 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.opps[i] = dce112_opp_create( opps 1284 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.opps[i] == NULL) { opps 553 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.opps[i] != NULL) opps 554 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce110_opp_destroy(&pool->base.opps[i]); opps 1131 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.opps[j] = dce120_opp_create( opps 1134 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.opps[j] == NULL) { opps 735 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] != NULL) opps 736 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce110_opp_destroy(&pool->base.opps[i]); opps 1000 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.opps[i] = dce80_opp_create(ctx, i); opps 1001 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] == NULL) { opps 1197 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.opps[i] = dce80_opp_create(ctx, i); opps 1198 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] == NULL) { opps 1390 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.opps[i] = dce80_opp_create(ctx, i); opps 1391 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] == NULL) { opps 1156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; opps 1157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; opps 1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; opps 1159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; opps 907 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.opps[i] != NULL) opps 908 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); opps 1478 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.opps[j] = dcn10_opp_create(ctx, i); opps 1479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.opps[j] == NULL) { opps 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp = dc->res_pool->opps[opp_id_src0]; opps 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bottom_opp = dc->res_pool->opps[opp_id_src1]; opps 2049 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; opps 2050 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c res_pool->opps[i]->mpc_tree_params.opp_list = NULL; opps 2052 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c res_pool->opps[i]->mpcc_disconnect_pending[j] = false; opps 2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; opps 2077 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; opps 1361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.opps[i] != NULL) opps 1362 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); opps 1787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; opps 3662 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.opps[i] = dcn20_opp_create(ctx, i); opps 3663 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.opps[i] == NULL) { opps 889 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.opps[i] != NULL) opps 890 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); opps 1592 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.opps[i] = dcn21_opp_create(ctx, i); opps 1593 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.opps[i] == NULL) { opps 170 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct output_pixel_processor *opps[MAX_PIPES]; opps 1875 drivers/mfd/db8500-prcmu.c u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP }; opps 1899 drivers/mfd/db8500-prcmu.c pr_debug("SET ARM OPP 0x%02x\n", opps[i]); opps 1900 drivers/mfd/db8500-prcmu.c return db8500_prcmu_set_arm_opp(opps[i]); opps 17 include/linux/scpi_protocol.h struct scpi_opp *opps; opps 158 net/ipv6/ip6_offload.c const struct net_offload **opps) opps 166 net/ipv6/ip6_offload.c *opps = rcu_dereference(inet6_offloads[proto]); opps 167 net/ipv6/ip6_offload.c if (unlikely(!(*opps))) opps 169 net/ipv6/ip6_offload.c if (!((*opps)->flags & INET6_PROTO_GSO_EXTHDR))