oppn20             31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	(oppn20->regs->reg)
oppn20             35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->opp_shift->field_name, oppn20->opp_mask->field_name
oppn20             38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->base.ctx
oppn20             49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
oppn20            277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
oppn20            294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
oppn20            313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
oppn20            339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c void dcn20_opp_construct(struct dcn20_opp *oppn20,
oppn20            346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->base.ctx = ctx;
oppn20            347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->base.inst = inst;
oppn20            348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->base.funcs = &dcn20_opp_funcs;
oppn20            350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->regs = regs;
oppn20            351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->opp_shift = opp_shift;
oppn20            352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	oppn20->opp_mask = opp_mask;
oppn20            133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h void dcn20_opp_construct(struct dcn20_opp *oppn20,