opp_mask 40 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp110->opp_shift->field_name, opp110->opp_mask->field_name opp_mask 185 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c if (opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX && opp_mask 186 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP) { opp_mask 387 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c if (opp110->opp_mask->FMT_CBCR_BIT_REDUCTION_BYPASS) opp_mask 549 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c const struct dce_opp_mask *opp_mask) opp_mask 559 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp110->opp_mask = opp_mask; opp_mask 272 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h const struct dce_opp_mask *opp_mask; opp_mask 280 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h const struct dce_opp_mask *opp_mask); opp_mask 270 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c static const struct dce_opp_mask opp_mask = { opp_mask 598 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); opp_mask 296 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static const struct dce_opp_mask opp_mask = { opp_mask 644 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); opp_mask 303 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c static const struct dce_opp_mask opp_mask = { opp_mask 617 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); opp_mask 314 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static const struct dce_opp_mask opp_mask = { opp_mask 392 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); opp_mask 287 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c static const struct dce_opp_mask opp_mask = { opp_mask 478 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); opp_mask 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c oppn10->opp_shift->field_name, oppn10->opp_mask->field_name opp_mask 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c const struct dcn10_opp_mask *opp_mask) opp_mask 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c oppn10->opp_mask = opp_mask; opp_mask 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h const struct dcn10_opp_mask *opp_mask; opp_mask 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h const struct dcn10_opp_mask *opp_mask); opp_mask 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn10_opp_mask opp_mask = { opp_mask 629 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &opp_regs[inst], &opp_shift, &opp_mask); opp_mask 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c oppn20->opp_shift->field_name, oppn20->opp_mask->field_name opp_mask 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c const struct dcn20_opp_mask *opp_mask) opp_mask 352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c oppn20->opp_mask = opp_mask; opp_mask 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h const struct dcn20_opp_mask *opp_mask; opp_mask 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h const struct dcn20_opp_mask *opp_mask); opp_mask 659 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn20_opp_mask opp_mask = { opp_mask 1020 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &opp_regs[inst], &opp_shift, &opp_mask); opp_mask 425 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn20_opp_mask opp_mask = { opp_mask 1204 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &opp_regs[inst], &opp_shift, &opp_mask);