opp_id 2665 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c int opp_id) opp_id 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp->opp_id = OPP_ID_INVALID; opp_id 1267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.opp_id = OPP_ID_INVALID; opp_id 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (s.opp_id != 0xf) opp_id 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c i, s.opp_id, s.dpp_id, s.bot_mpcc_id, opp_id 1033 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int opp_id = hubp->opp_id; opp_id 1041 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) opp_id 1153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->opp_id = OPP_ID_INVALID; opp_id 1156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; opp_id 1946 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int opp_id) opp_id 2263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; opp_id 2608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) opp_id 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if (s.opp_id != 0xf) { opp_id 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c i, s.opp_id, s.dpp_id, s.bot_mpcc_id, opp_id 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c unsigned int opp_id; opp_id 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); opp_id 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (top_sel == 0xf && opp_id == 0xf && idle) opp_id 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); opp_id 223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); opp_id 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); opp_id 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); opp_id 350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int opp_id; opp_id 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { opp_id 362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (REG(MUX[opp_id])) opp_id 363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); opp_id 370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c int opp_id; opp_id 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); opp_id 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (opp_id < MAX_OPP && REG(MUX[opp_id])) opp_id 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf); opp_id 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c unsigned int opp_id; opp_id 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); opp_id 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); opp_id 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { opp_id 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); opp_id 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if ((opp_id == tree->opp_id) && (top_sel != 0xf)) { opp_id 438 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); opp_id 934 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp->opp_id = OPP_ID_INVALID; opp_id 1286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.opp_id = OPP_ID_INVALID; opp_id 627 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int opp_id) opp_id 639 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp_id, opp_id 645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp_id, opp_id 1206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) opp_id 1799 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; opp_id 2049 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; opp_id 2068 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->opp_id = OPP_ID_INVALID; opp_id 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h int opp_id); opp_id 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c int opp_id, opp_id 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_UPDATE(DENORM_CONTROL[opp_id], opp_id 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c int opp_id, opp_id 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_UPDATE_2(DENORM_CONTROL[opp_id], opp_id 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], opp_id 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], opp_id 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c int opp_id, opp_id 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); opp_id 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); opp_id 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); opp_id 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); opp_id 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); opp_id 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c int opp_id, opp_id 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); opp_id 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); opp_id 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); opp_id 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); opp_id 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); opp_id 261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h int opp_id, opp_id 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h int opp_id, opp_id 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h int opp_id, opp_id 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h int opp_id, opp_id 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, opp_id 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); opp_id 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OPTC_SEG0_SRC_SEL, opp_id[0], opp_id 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OPTC_SEG1_SRC_SEL, opp_id[1]); opp_id 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, opp_id 240 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.opp_id = OPP_ID_INVALID; opp_id 62 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h int opp_id; opp_id 120 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int opp_id; /* The OPP instance that owns this MPC tree */ opp_id 136 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h uint32_t opp_id; opp_id 235 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int opp_id, opp_id 240 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int opp_id, opp_id 244 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int opp_id, opp_id 249 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h int opp_id, opp_id 276 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, opp_id 114 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h int opp_id);