opp 457 arch/arm/mach-davinci/da850.c struct da850_opp *opp; opp 462 arch/arm/mach-davinci/da850.c opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; opp 464 arch/arm/mach-davinci/da850.c return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); opp 848 arch/powerpc/include/asm/kvm_ppc.h void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu); opp 862 arch/powerpc/include/asm/kvm_ppc.h static inline void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, opp 129 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ, opp 172 arch/powerpc/kvm/mpic.c #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) opp 242 arch/powerpc/kvm/mpic.c static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst, opp 251 arch/powerpc/kvm/mpic.c __func__, (int)(dst - &opp->dst[0])); opp 264 arch/powerpc/kvm/mpic.c static void mpic_irq_lower(struct openpic *opp, struct irq_dest *dst, opp 269 arch/powerpc/kvm/mpic.c __func__, (int)(dst - &opp->dst[0])); opp 292 arch/powerpc/kvm/mpic.c static void IRQ_check(struct openpic *opp, struct irq_queue *q) opp 299 arch/powerpc/kvm/mpic.c irq = find_next_bit(q->queue, opp->max_irq, irq + 1); opp 300 arch/powerpc/kvm/mpic.c if (irq == opp->max_irq) opp 304 arch/powerpc/kvm/mpic.c irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); opp 306 arch/powerpc/kvm/mpic.c if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { opp 308 arch/powerpc/kvm/mpic.c priority = IVPR_PRIORITY(opp->src[irq].ivpr); opp 316 arch/powerpc/kvm/mpic.c static int IRQ_get_next(struct openpic *opp, struct irq_queue *q) opp 319 arch/powerpc/kvm/mpic.c IRQ_check(opp, q); opp 324 arch/powerpc/kvm/mpic.c static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ, opp 331 arch/powerpc/kvm/mpic.c dst = &opp->dst[n_CPU]; opp 332 arch/powerpc/kvm/mpic.c src = &opp->src[n_IRQ]; opp 351 arch/powerpc/kvm/mpic.c mpic_irq_raise(opp, dst, src->output); opp 358 arch/powerpc/kvm/mpic.c mpic_irq_lower(opp, dst, src->output); opp 375 arch/powerpc/kvm/mpic.c IRQ_check(opp, &dst->raised); opp 384 arch/powerpc/kvm/mpic.c if (IRQ_get_next(opp, &dst->servicing) >= 0 && opp 391 arch/powerpc/kvm/mpic.c mpic_irq_raise(opp, dst, ILR_INTTGT_INT); opp 394 arch/powerpc/kvm/mpic.c IRQ_get_next(opp, &dst->servicing); opp 406 arch/powerpc/kvm/mpic.c mpic_irq_lower(opp, dst, ILR_INTTGT_INT); opp 412 arch/powerpc/kvm/mpic.c static void openpic_update_irq(struct openpic *opp, int n_IRQ) opp 418 arch/powerpc/kvm/mpic.c src = &opp->src[n_IRQ]; opp 451 arch/powerpc/kvm/mpic.c IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); opp 454 arch/powerpc/kvm/mpic.c for (i = 0; i < opp->nb_cpus; i++) { opp 456 arch/powerpc/kvm/mpic.c IRQ_local_pipe(opp, i, n_IRQ, active, opp 463 arch/powerpc/kvm/mpic.c if (i == opp->nb_cpus) opp 467 arch/powerpc/kvm/mpic.c IRQ_local_pipe(opp, i, n_IRQ, active, opp 478 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 486 arch/powerpc/kvm/mpic.c src = &opp->src[n_IRQ]; opp 492 arch/powerpc/kvm/mpic.c openpic_update_irq(opp, n_IRQ); opp 497 arch/powerpc/kvm/mpic.c openpic_update_irq(opp, n_IRQ); opp 508 arch/powerpc/kvm/mpic.c openpic_update_irq(opp, n_IRQ); opp 513 arch/powerpc/kvm/mpic.c static void openpic_reset(struct openpic *opp) opp 517 arch/powerpc/kvm/mpic.c opp->gcr = GCR_RESET; opp 519 arch/powerpc/kvm/mpic.c opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) | opp 520 arch/powerpc/kvm/mpic.c (opp->vid << FRR_VID_SHIFT); opp 522 arch/powerpc/kvm/mpic.c opp->pir = 0; opp 523 arch/powerpc/kvm/mpic.c opp->spve = -1 & opp->vector_mask; opp 524 arch/powerpc/kvm/mpic.c opp->tfrr = opp->tfrr_reset; opp 526 arch/powerpc/kvm/mpic.c for (i = 0; i < opp->max_irq; i++) { opp 527 arch/powerpc/kvm/mpic.c opp->src[i].ivpr = opp->ivpr_reset; opp 529 arch/powerpc/kvm/mpic.c switch (opp->src[i].type) { opp 531 arch/powerpc/kvm/mpic.c opp->src[i].level = opp 532 arch/powerpc/kvm/mpic.c !!(opp->ivpr_reset & IVPR_SENSE_MASK); opp 536 arch/powerpc/kvm/mpic.c opp->src[i].ivpr |= IVPR_POLARITY_MASK; opp 543 arch/powerpc/kvm/mpic.c write_IRQreg_idr(opp, i, opp->idr_reset); opp 547 arch/powerpc/kvm/mpic.c opp->dst[i].ctpr = 15; opp 548 arch/powerpc/kvm/mpic.c memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue)); opp 549 arch/powerpc/kvm/mpic.c opp->dst[i].raised.next = -1; opp 550 arch/powerpc/kvm/mpic.c memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue)); opp 551 arch/powerpc/kvm/mpic.c opp->dst[i].servicing.next = -1; opp 555 arch/powerpc/kvm/mpic.c opp->timers[i].tccr = 0; opp 556 arch/powerpc/kvm/mpic.c opp->timers[i].tbcr = TBCR_CI; opp 559 arch/powerpc/kvm/mpic.c opp->gcr = 0; opp 562 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ) opp 564 arch/powerpc/kvm/mpic.c return opp->src[n_IRQ].idr; opp 567 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ) opp 569 arch/powerpc/kvm/mpic.c if (opp->flags & OPENPIC_FLAG_ILR) opp 570 arch/powerpc/kvm/mpic.c return opp->src[n_IRQ].output; opp 575 arch/powerpc/kvm/mpic.c static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ) opp 577 arch/powerpc/kvm/mpic.c return opp->src[n_IRQ].ivpr; opp 580 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ, opp 583 arch/powerpc/kvm/mpic.c struct irq_source *src = &opp->src[n_IRQ]; opp 584 arch/powerpc/kvm/mpic.c uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; opp 587 arch/powerpc/kvm/mpic.c int crit_shift = IDR_EP_SHIFT - opp->nb_cpus; opp 590 arch/powerpc/kvm/mpic.c if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { opp 598 arch/powerpc/kvm/mpic.c if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { opp 609 arch/powerpc/kvm/mpic.c for (i = 0; i < opp->nb_cpus; i++) { opp 625 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ, opp 628 arch/powerpc/kvm/mpic.c if (opp->flags & OPENPIC_FLAG_ILR) { opp 629 arch/powerpc/kvm/mpic.c struct irq_source *src = &opp->src[n_IRQ]; opp 639 arch/powerpc/kvm/mpic.c static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ, opp 648 arch/powerpc/kvm/mpic.c IVPR_POLARITY_MASK | opp->vector_mask; opp 651 arch/powerpc/kvm/mpic.c opp->src[n_IRQ].ivpr = opp 652 arch/powerpc/kvm/mpic.c (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); opp 658 arch/powerpc/kvm/mpic.c switch (opp->src[n_IRQ].type) { opp 660 arch/powerpc/kvm/mpic.c opp->src[n_IRQ].level = opp 661 arch/powerpc/kvm/mpic.c !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); opp 665 arch/powerpc/kvm/mpic.c opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; opp 669 arch/powerpc/kvm/mpic.c opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); opp 673 arch/powerpc/kvm/mpic.c openpic_update_irq(opp, n_IRQ); opp 675 arch/powerpc/kvm/mpic.c opp->src[n_IRQ].ivpr); opp 678 arch/powerpc/kvm/mpic.c static void openpic_gcr_write(struct openpic *opp, uint64_t val) opp 681 arch/powerpc/kvm/mpic.c openpic_reset(opp); opp 685 arch/powerpc/kvm/mpic.c opp->gcr &= ~opp->mpic_mode_mask; opp 686 arch/powerpc/kvm/mpic.c opp->gcr |= val & opp->mpic_mode_mask; opp 691 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 709 arch/powerpc/kvm/mpic.c err = openpic_cpu_write_internal(opp, addr, val, opp 715 arch/powerpc/kvm/mpic.c openpic_gcr_write(opp, val); opp 732 arch/powerpc/kvm/mpic.c write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); opp 736 arch/powerpc/kvm/mpic.c opp->spve = val & opp->vector_mask; opp 747 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 758 arch/powerpc/kvm/mpic.c retval = opp->frr; opp 759 arch/powerpc/kvm/mpic.c retval |= (opp->nb_cpus - 1) << FRR_NCPU_SHIFT; opp 762 arch/powerpc/kvm/mpic.c retval = opp->gcr; opp 765 arch/powerpc/kvm/mpic.c retval = opp->vir; opp 771 arch/powerpc/kvm/mpic.c retval = opp->brr1; opp 781 arch/powerpc/kvm/mpic.c err = openpic_cpu_read_internal(opp, addr, opp 791 arch/powerpc/kvm/mpic.c retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx); opp 795 arch/powerpc/kvm/mpic.c retval = opp->spve; opp 809 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 820 arch/powerpc/kvm/mpic.c opp->tfrr = val; opp 831 arch/powerpc/kvm/mpic.c if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && opp 833 arch/powerpc/kvm/mpic.c (opp->timers[idx].tbcr & TBCR_CI) != 0) opp 834 arch/powerpc/kvm/mpic.c opp->timers[idx].tccr &= ~TCCR_TOG; opp 836 arch/powerpc/kvm/mpic.c opp->timers[idx].tbcr = val; opp 839 arch/powerpc/kvm/mpic.c write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val); opp 842 arch/powerpc/kvm/mpic.c write_IRQreg_idr(opp, opp->irq_tim0 + idx, val); opp 851 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 862 arch/powerpc/kvm/mpic.c retval = opp->tfrr; opp 868 arch/powerpc/kvm/mpic.c retval = opp->timers[idx].tccr; opp 871 arch/powerpc/kvm/mpic.c retval = opp->timers[idx].tbcr; opp 874 arch/powerpc/kvm/mpic.c retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); opp 877 arch/powerpc/kvm/mpic.c retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx); opp 889 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 899 arch/powerpc/kvm/mpic.c write_IRQreg_ivpr(opp, idx, val); opp 902 arch/powerpc/kvm/mpic.c write_IRQreg_idr(opp, idx, val); opp 905 arch/powerpc/kvm/mpic.c write_IRQreg_ilr(opp, idx, val); opp 914 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 926 arch/powerpc/kvm/mpic.c retval = read_IRQreg_ivpr(opp, idx); opp 929 arch/powerpc/kvm/mpic.c retval = read_IRQreg_idr(opp, idx); opp 932 arch/powerpc/kvm/mpic.c retval = read_IRQreg_ilr(opp, idx); opp 943 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 944 arch/powerpc/kvm/mpic.c int idx = opp->irq_msi; opp 956 arch/powerpc/kvm/mpic.c opp->msi[srs].msir |= 1 << ibs; opp 957 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, idx, 1); opp 969 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 988 arch/powerpc/kvm/mpic.c r = opp->msi[srs].msir; opp 990 arch/powerpc/kvm/mpic.c opp->msi[srs].msir = 0; opp 991 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, opp->irq_msi + srs, 0); opp 995 arch/powerpc/kvm/mpic.c r |= (opp->msi[i].msir ? 1 : 0) << i; opp 1027 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 1041 arch/powerpc/kvm/mpic.c dst = &opp->dst[idx]; opp 1050 arch/powerpc/kvm/mpic.c opp->src[opp->irq_ipi0 + idx].destmask |= val; opp 1051 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); opp 1052 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); opp 1064 arch/powerpc/kvm/mpic.c mpic_irq_lower(opp, dst, ILR_INTTGT_INT); opp 1068 arch/powerpc/kvm/mpic.c mpic_irq_raise(opp, dst, ILR_INTTGT_INT); opp 1082 arch/powerpc/kvm/mpic.c s_IRQ = IRQ_get_next(opp, &dst->servicing); opp 1094 arch/powerpc/kvm/mpic.c s_IRQ = IRQ_get_next(opp, &dst->servicing); opp 1096 arch/powerpc/kvm/mpic.c n_IRQ = IRQ_get_next(opp, &dst->raised); opp 1097 arch/powerpc/kvm/mpic.c src = &opp->src[n_IRQ]; opp 1103 arch/powerpc/kvm/mpic.c mpic_irq_raise(opp, dst, ILR_INTTGT_INT); opp 1106 arch/powerpc/kvm/mpic.c spin_unlock(&opp->lock); opp 1107 arch/powerpc/kvm/mpic.c kvm_notify_acked_irq(opp->kvm, 0, notify_eoi); opp 1108 arch/powerpc/kvm/mpic.c spin_lock(&opp->lock); opp 1121 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 1123 arch/powerpc/kvm/mpic.c return openpic_cpu_write_internal(opp, addr, val, opp 1127 arch/powerpc/kvm/mpic.c static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst, opp 1134 arch/powerpc/kvm/mpic.c mpic_irq_lower(opp, dst, ILR_INTTGT_INT); opp 1136 arch/powerpc/kvm/mpic.c irq = IRQ_get_next(opp, &dst->raised); opp 1141 arch/powerpc/kvm/mpic.c return opp->spve; opp 1143 arch/powerpc/kvm/mpic.c src = &opp->src[irq]; opp 1148 arch/powerpc/kvm/mpic.c openpic_update_irq(opp, irq); opp 1149 arch/powerpc/kvm/mpic.c retval = opp->spve; opp 1153 arch/powerpc/kvm/mpic.c retval = IVPR_VECTOR(opp, src->ivpr); opp 1163 arch/powerpc/kvm/mpic.c if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) { opp 1167 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, irq, 1); opp 1168 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, irq, 0); opp 1179 arch/powerpc/kvm/mpic.c struct openpic *opp = vcpu->arch.mpic; opp 1183 arch/powerpc/kvm/mpic.c spin_lock_irqsave(&opp->lock, flags); opp 1185 arch/powerpc/kvm/mpic.c if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY) opp 1186 arch/powerpc/kvm/mpic.c kvmppc_set_epr(vcpu, openpic_iack(opp, &opp->dst[cpu], cpu)); opp 1188 arch/powerpc/kvm/mpic.c spin_unlock_irqrestore(&opp->lock, flags); opp 1194 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 1207 arch/powerpc/kvm/mpic.c dst = &opp->dst[idx]; opp 1217 arch/powerpc/kvm/mpic.c retval = openpic_iack(opp, dst, idx); opp 1234 arch/powerpc/kvm/mpic.c struct openpic *opp = opaque; opp 1236 arch/powerpc/kvm/mpic.c return openpic_cpu_read_internal(opp, addr, ptr, opp 1289 arch/powerpc/kvm/mpic.c static void add_mmio_region(struct openpic *opp, const struct mem_reg *mr) opp 1291 arch/powerpc/kvm/mpic.c if (opp->num_mmio_regions >= MAX_MMIO_REGIONS) { opp 1296 arch/powerpc/kvm/mpic.c opp->mmio_regions[opp->num_mmio_regions++] = mr; opp 1299 arch/powerpc/kvm/mpic.c static void fsl_common_init(struct openpic *opp) opp 1304 arch/powerpc/kvm/mpic.c add_mmio_region(opp, &openpic_msi_mmio); opp 1305 arch/powerpc/kvm/mpic.c add_mmio_region(opp, &openpic_summary_mmio); opp 1307 arch/powerpc/kvm/mpic.c opp->vid = VID_REVISION_1_2; opp 1308 arch/powerpc/kvm/mpic.c opp->vir = VIR_GENERIC; opp 1309 arch/powerpc/kvm/mpic.c opp->vector_mask = 0xFFFF; opp 1310 arch/powerpc/kvm/mpic.c opp->tfrr_reset = 0; opp 1311 arch/powerpc/kvm/mpic.c opp->ivpr_reset = IVPR_MASK_MASK; opp 1312 arch/powerpc/kvm/mpic.c opp->idr_reset = 1 << 0; opp 1313 arch/powerpc/kvm/mpic.c opp->max_irq = MAX_IRQ; opp 1315 arch/powerpc/kvm/mpic.c opp->irq_ipi0 = virq; opp 1317 arch/powerpc/kvm/mpic.c opp->irq_tim0 = virq; opp 1322 arch/powerpc/kvm/mpic.c opp->irq_msi = 224; opp 1324 arch/powerpc/kvm/mpic.c for (i = 0; i < opp->fsl->max_ext; i++) opp 1325 arch/powerpc/kvm/mpic.c opp->src[i].level = false; opp 1329 arch/powerpc/kvm/mpic.c opp->src[i].type = IRQ_TYPE_FSLINT; opp 1330 arch/powerpc/kvm/mpic.c opp->src[i].level = true; opp 1335 arch/powerpc/kvm/mpic.c opp->src[i].type = IRQ_TYPE_FSLSPECIAL; opp 1336 arch/powerpc/kvm/mpic.c opp->src[i].level = false; opp 1340 arch/powerpc/kvm/mpic.c static int kvm_mpic_read_internal(struct openpic *opp, gpa_t addr, u32 *ptr) opp 1344 arch/powerpc/kvm/mpic.c for (i = 0; i < opp->num_mmio_regions; i++) { opp 1345 arch/powerpc/kvm/mpic.c const struct mem_reg *mr = opp->mmio_regions[i]; opp 1350 arch/powerpc/kvm/mpic.c return mr->read(opp, addr - mr->start_addr, ptr); opp 1356 arch/powerpc/kvm/mpic.c static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val) opp 1360 arch/powerpc/kvm/mpic.c for (i = 0; i < opp->num_mmio_regions; i++) { opp 1361 arch/powerpc/kvm/mpic.c const struct mem_reg *mr = opp->mmio_regions[i]; opp 1366 arch/powerpc/kvm/mpic.c return mr->write(opp, addr - mr->start_addr, val); opp 1376 arch/powerpc/kvm/mpic.c struct openpic *opp = container_of(this, struct openpic, mmio); opp 1389 arch/powerpc/kvm/mpic.c spin_lock_irq(&opp->lock); opp 1390 arch/powerpc/kvm/mpic.c ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); opp 1391 arch/powerpc/kvm/mpic.c spin_unlock_irq(&opp->lock); opp 1418 arch/powerpc/kvm/mpic.c struct openpic *opp = container_of(this, struct openpic, mmio); opp 1430 arch/powerpc/kvm/mpic.c spin_lock_irq(&opp->lock); opp 1431 arch/powerpc/kvm/mpic.c ret = kvm_mpic_write_internal(opp, addr - opp->reg_base, opp 1433 arch/powerpc/kvm/mpic.c spin_unlock_irq(&opp->lock); opp 1446 arch/powerpc/kvm/mpic.c static void map_mmio(struct openpic *opp) opp 1448 arch/powerpc/kvm/mpic.c kvm_iodevice_init(&opp->mmio, &mpic_mmio_ops); opp 1450 arch/powerpc/kvm/mpic.c kvm_io_bus_register_dev(opp->kvm, KVM_MMIO_BUS, opp 1451 arch/powerpc/kvm/mpic.c opp->reg_base, OPENPIC_REG_SIZE, opp 1452 arch/powerpc/kvm/mpic.c &opp->mmio); opp 1455 arch/powerpc/kvm/mpic.c static void unmap_mmio(struct openpic *opp) opp 1457 arch/powerpc/kvm/mpic.c kvm_io_bus_unregister_dev(opp->kvm, KVM_MMIO_BUS, &opp->mmio); opp 1460 arch/powerpc/kvm/mpic.c static int set_base_addr(struct openpic *opp, struct kvm_device_attr *attr) opp 1473 arch/powerpc/kvm/mpic.c if (base == opp->reg_base) opp 1476 arch/powerpc/kvm/mpic.c mutex_lock(&opp->kvm->slots_lock); opp 1478 arch/powerpc/kvm/mpic.c unmap_mmio(opp); opp 1479 arch/powerpc/kvm/mpic.c opp->reg_base = base; opp 1487 arch/powerpc/kvm/mpic.c map_mmio(opp); opp 1490 arch/powerpc/kvm/mpic.c mutex_unlock(&opp->kvm->slots_lock); opp 1497 arch/powerpc/kvm/mpic.c static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type) opp 1504 arch/powerpc/kvm/mpic.c spin_lock_irq(&opp->lock); opp 1507 arch/powerpc/kvm/mpic.c ret = kvm_mpic_write_internal(opp, addr, *val); opp 1509 arch/powerpc/kvm/mpic.c ret = kvm_mpic_read_internal(opp, addr, val); opp 1511 arch/powerpc/kvm/mpic.c spin_unlock_irq(&opp->lock); opp 1520 arch/powerpc/kvm/mpic.c struct openpic *opp = dev->private; opp 1527 arch/powerpc/kvm/mpic.c return set_base_addr(opp, attr); opp 1536 arch/powerpc/kvm/mpic.c return access_reg(opp, attr->attr, &attr32, ATTR_SET); opp 1548 arch/powerpc/kvm/mpic.c spin_lock_irq(&opp->lock); opp 1549 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, attr->attr, attr32); opp 1550 arch/powerpc/kvm/mpic.c spin_unlock_irq(&opp->lock); opp 1559 arch/powerpc/kvm/mpic.c struct openpic *opp = dev->private; opp 1568 arch/powerpc/kvm/mpic.c mutex_lock(&opp->kvm->slots_lock); opp 1569 arch/powerpc/kvm/mpic.c attr64 = opp->reg_base; opp 1570 arch/powerpc/kvm/mpic.c mutex_unlock(&opp->kvm->slots_lock); opp 1582 arch/powerpc/kvm/mpic.c ret = access_reg(opp, attr->attr, &attr32, ATTR_GET); opp 1595 arch/powerpc/kvm/mpic.c spin_lock_irq(&opp->lock); opp 1596 arch/powerpc/kvm/mpic.c attr32 = opp->src[attr->attr].pending; opp 1597 arch/powerpc/kvm/mpic.c spin_unlock_irq(&opp->lock); opp 1634 arch/powerpc/kvm/mpic.c struct openpic *opp = dev->private; opp 1637 arch/powerpc/kvm/mpic.c kfree(opp); opp 1641 arch/powerpc/kvm/mpic.c static int mpic_set_default_irq_routing(struct openpic *opp) opp 1650 arch/powerpc/kvm/mpic.c kvm_set_irq_routing(opp->kvm, routing, 0, 0); opp 1658 arch/powerpc/kvm/mpic.c struct openpic *opp; opp 1665 arch/powerpc/kvm/mpic.c opp = kzalloc(sizeof(struct openpic), GFP_KERNEL); opp 1666 arch/powerpc/kvm/mpic.c if (!opp) opp 1669 arch/powerpc/kvm/mpic.c dev->private = opp; opp 1670 arch/powerpc/kvm/mpic.c opp->kvm = dev->kvm; opp 1671 arch/powerpc/kvm/mpic.c opp->dev = dev; opp 1672 arch/powerpc/kvm/mpic.c opp->model = type; opp 1673 arch/powerpc/kvm/mpic.c spin_lock_init(&opp->lock); opp 1675 arch/powerpc/kvm/mpic.c add_mmio_region(opp, &openpic_gbl_mmio); opp 1676 arch/powerpc/kvm/mpic.c add_mmio_region(opp, &openpic_tmr_mmio); opp 1677 arch/powerpc/kvm/mpic.c add_mmio_region(opp, &openpic_src_mmio); opp 1678 arch/powerpc/kvm/mpic.c add_mmio_region(opp, &openpic_cpu_mmio); opp 1680 arch/powerpc/kvm/mpic.c switch (opp->model) { opp 1682 arch/powerpc/kvm/mpic.c opp->fsl = &fsl_mpic_20; opp 1683 arch/powerpc/kvm/mpic.c opp->brr1 = 0x00400200; opp 1684 arch/powerpc/kvm/mpic.c opp->flags |= OPENPIC_FLAG_IDR_CRIT; opp 1685 arch/powerpc/kvm/mpic.c opp->nb_irqs = 80; opp 1686 arch/powerpc/kvm/mpic.c opp->mpic_mode_mask = GCR_MODE_MIXED; opp 1688 arch/powerpc/kvm/mpic.c fsl_common_init(opp); opp 1693 arch/powerpc/kvm/mpic.c opp->fsl = &fsl_mpic_42; opp 1694 arch/powerpc/kvm/mpic.c opp->brr1 = 0x00400402; opp 1695 arch/powerpc/kvm/mpic.c opp->flags |= OPENPIC_FLAG_ILR; opp 1696 arch/powerpc/kvm/mpic.c opp->nb_irqs = 196; opp 1697 arch/powerpc/kvm/mpic.c opp->mpic_mode_mask = GCR_MODE_PROXY; opp 1699 arch/powerpc/kvm/mpic.c fsl_common_init(opp); opp 1708 arch/powerpc/kvm/mpic.c ret = mpic_set_default_irq_routing(opp); opp 1712 arch/powerpc/kvm/mpic.c openpic_reset(opp); opp 1715 arch/powerpc/kvm/mpic.c dev->kvm->arch.mpic = opp; opp 1720 arch/powerpc/kvm/mpic.c kfree(opp); opp 1736 arch/powerpc/kvm/mpic.c struct openpic *opp = dev->private; opp 1741 arch/powerpc/kvm/mpic.c if (opp->kvm != vcpu->kvm) opp 1746 arch/powerpc/kvm/mpic.c spin_lock_irq(&opp->lock); opp 1748 arch/powerpc/kvm/mpic.c if (opp->dst[cpu].vcpu) { opp 1757 arch/powerpc/kvm/mpic.c opp->dst[cpu].vcpu = vcpu; opp 1758 arch/powerpc/kvm/mpic.c opp->nb_cpus = max(opp->nb_cpus, cpu + 1); opp 1760 arch/powerpc/kvm/mpic.c vcpu->arch.mpic = opp; opp 1765 arch/powerpc/kvm/mpic.c if (opp->mpic_mode_mask == GCR_MODE_PROXY) opp 1769 arch/powerpc/kvm/mpic.c spin_unlock_irq(&opp->lock); opp 1778 arch/powerpc/kvm/mpic.c void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu) opp 1780 arch/powerpc/kvm/mpic.c BUG_ON(!opp->dst[vcpu->arch.irq_cpu_id].vcpu); opp 1782 arch/powerpc/kvm/mpic.c opp->dst[vcpu->arch.irq_cpu_id].vcpu = NULL; opp 1796 arch/powerpc/kvm/mpic.c struct openpic *opp = kvm->arch.mpic; opp 1799 arch/powerpc/kvm/mpic.c spin_lock_irqsave(&opp->lock, flags); opp 1800 arch/powerpc/kvm/mpic.c openpic_set_irq(opp, irq, level); opp 1801 arch/powerpc/kvm/mpic.c spin_unlock_irqrestore(&opp->lock, flags); opp 1810 arch/powerpc/kvm/mpic.c struct openpic *opp = kvm->arch.mpic; opp 1813 arch/powerpc/kvm/mpic.c spin_lock_irqsave(&opp->lock, flags); opp 1820 arch/powerpc/kvm/mpic.c spin_unlock_irqrestore(&opp->lock, flags); opp 2699 drivers/base/power/domain.c struct dev_pm_opp *opp) opp 2710 drivers/base/power/domain.c state = genpd->opp_to_performance_state(genpd, opp); opp 67 drivers/clk/clk-scpi.c const struct scpi_opp *opp = clk->info->opps; opp 69 drivers/clk/clk-scpi.c for (idx = 0; idx < clk->info->count; idx++, opp++) { opp 70 drivers/clk/clk-scpi.c ftmp = opp->freq; opp 87 drivers/clk/clk-scpi.c const struct scpi_opp *opp; opp 92 drivers/clk/clk-scpi.c opp = clk->info->opps + idx; opp 93 drivers/clk/clk-scpi.c return opp->freq; opp 107 drivers/clk/clk-scpi.c const struct scpi_opp *opp = clk->info->opps; opp 109 drivers/clk/clk-scpi.c for (idx = 0; idx < max_opp; idx++, opp++) opp 110 drivers/clk/clk-scpi.c if (opp->freq == rate) opp 505 drivers/clk/tegra/clk-dfll.c struct dev_pm_opp *opp; opp 511 drivers/clk/tegra/clk-dfll.c opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); opp 512 drivers/clk/tegra/clk-dfll.c if (IS_ERR(opp)) opp 515 drivers/clk/tegra/clk-dfll.c uv = dev_pm_opp_get_voltage(opp); opp 516 drivers/clk/tegra/clk-dfll.c dev_pm_opp_put(opp); opp 797 drivers/clk/tegra/clk-dfll.c struct dev_pm_opp *opp; opp 800 drivers/clk/tegra/clk-dfll.c opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); opp 801 drivers/clk/tegra/clk-dfll.c if (IS_ERR(opp)) opp 802 drivers/clk/tegra/clk-dfll.c return PTR_ERR(opp); opp 804 drivers/clk/tegra/clk-dfll.c align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv; opp 805 drivers/clk/tegra/clk-dfll.c dev_pm_opp_put(opp); opp 1654 drivers/clk/tegra/clk-dfll.c struct dev_pm_opp *opp; opp 1656 drivers/clk/tegra/clk-dfll.c opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); opp 1657 drivers/clk/tegra/clk-dfll.c if (IS_ERR(opp)) opp 1659 drivers/clk/tegra/clk-dfll.c v_opp = dev_pm_opp_get_voltage(opp); opp 1662 drivers/clk/tegra/clk-dfll.c td->dvco_rate_min = dev_pm_opp_get_freq(opp); opp 1664 drivers/clk/tegra/clk-dfll.c dev_pm_opp_put(opp); opp 1708 drivers/clk/tegra/clk-dfll.c struct dev_pm_opp *opp; opp 1711 drivers/clk/tegra/clk-dfll.c opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); opp 1712 drivers/clk/tegra/clk-dfll.c if (IS_ERR(opp)) { opp 1716 drivers/clk/tegra/clk-dfll.c v_max = dev_pm_opp_get_voltage(opp); opp 1717 drivers/clk/tegra/clk-dfll.c dev_pm_opp_put(opp); opp 61 drivers/cpufreq/imx6q-cpufreq.c struct dev_pm_opp *opp; opp 71 drivers/cpufreq/imx6q-cpufreq.c opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); opp 72 drivers/cpufreq/imx6q-cpufreq.c if (IS_ERR(opp)) { opp 74 drivers/cpufreq/imx6q-cpufreq.c return PTR_ERR(opp); opp 77 drivers/cpufreq/imx6q-cpufreq.c volt = dev_pm_opp_get_voltage(opp); opp 78 drivers/cpufreq/imx6q-cpufreq.c dev_pm_opp_put(opp); opp 333 drivers/cpufreq/imx6q-cpufreq.c struct dev_pm_opp *opp; opp 479 drivers/cpufreq/imx6q-cpufreq.c opp = dev_pm_opp_find_freq_exact(cpu_dev, opp 481 drivers/cpufreq/imx6q-cpufreq.c min_volt = dev_pm_opp_get_voltage(opp); opp 482 drivers/cpufreq/imx6q-cpufreq.c dev_pm_opp_put(opp); opp 483 drivers/cpufreq/imx6q-cpufreq.c opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true); opp 484 drivers/cpufreq/imx6q-cpufreq.c max_volt = dev_pm_opp_get_voltage(opp); opp 485 drivers/cpufreq/imx6q-cpufreq.c dev_pm_opp_put(opp); opp 210 drivers/cpufreq/mediatek-cpufreq.c struct dev_pm_opp *opp; opp 225 drivers/cpufreq/mediatek-cpufreq.c opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); opp 226 drivers/cpufreq/mediatek-cpufreq.c if (IS_ERR(opp)) { opp 229 drivers/cpufreq/mediatek-cpufreq.c return PTR_ERR(opp); opp 231 drivers/cpufreq/mediatek-cpufreq.c vproc = dev_pm_opp_get_voltage(opp); opp 232 drivers/cpufreq/mediatek-cpufreq.c dev_pm_opp_put(opp); opp 307 drivers/cpufreq/mediatek-cpufreq.c struct dev_pm_opp *opp; opp 373 drivers/cpufreq/mediatek-cpufreq.c opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); opp 374 drivers/cpufreq/mediatek-cpufreq.c if (IS_ERR(opp)) { opp 376 drivers/cpufreq/mediatek-cpufreq.c ret = PTR_ERR(opp); opp 379 drivers/cpufreq/mediatek-cpufreq.c info->intermediate_voltage = dev_pm_opp_get_voltage(opp); opp 380 drivers/cpufreq/mediatek-cpufreq.c dev_pm_opp_put(opp); opp 45 drivers/cpufreq/omap-cpufreq.c struct dev_pm_opp *opp; opp 63 drivers/cpufreq/omap-cpufreq.c opp = dev_pm_opp_find_freq_ceil(mpu_dev, &freq); opp 64 drivers/cpufreq/omap-cpufreq.c if (IS_ERR(opp)) { opp 69 drivers/cpufreq/omap-cpufreq.c volt = dev_pm_opp_get_voltage(opp); opp 70 drivers/cpufreq/omap-cpufreq.c dev_pm_opp_put(opp); opp 75 drivers/devfreq/devfreq.c struct dev_pm_opp *opp; opp 78 drivers/devfreq/devfreq.c opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &min_freq); opp 79 drivers/devfreq/devfreq.c if (IS_ERR(opp)) opp 82 drivers/devfreq/devfreq.c dev_pm_opp_put(opp); opp 89 drivers/devfreq/devfreq.c struct dev_pm_opp *opp; opp 92 drivers/devfreq/devfreq.c opp = dev_pm_opp_find_freq_floor(devfreq->dev.parent, &max_freq); opp 93 drivers/devfreq/devfreq.c if (IS_ERR(opp)) opp 96 drivers/devfreq/devfreq.c dev_pm_opp_put(opp); opp 120 drivers/devfreq/devfreq.c struct dev_pm_opp *opp; opp 140 drivers/devfreq/devfreq.c opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &freq); opp 141 drivers/devfreq/devfreq.c if (IS_ERR(opp)) { opp 144 drivers/devfreq/devfreq.c return PTR_ERR(opp); opp 146 drivers/devfreq/devfreq.c dev_pm_opp_put(opp); opp 1506 drivers/devfreq/devfreq.c struct dev_pm_opp *opp; opp 1510 drivers/devfreq/devfreq.c opp = dev_pm_opp_find_freq_floor(dev, freq); opp 1513 drivers/devfreq/devfreq.c if (opp == ERR_PTR(-ERANGE)) opp 1514 drivers/devfreq/devfreq.c opp = dev_pm_opp_find_freq_ceil(dev, freq); opp 1517 drivers/devfreq/devfreq.c opp = dev_pm_opp_find_freq_ceil(dev, freq); opp 1520 drivers/devfreq/devfreq.c if (opp == ERR_PTR(-ERANGE)) opp 1521 drivers/devfreq/devfreq.c opp = dev_pm_opp_find_freq_floor(dev, freq); opp 1524 drivers/devfreq/devfreq.c return opp; opp 245 drivers/devfreq/exynos-bus.c struct dev_pm_opp *opp; opp 271 drivers/devfreq/exynos-bus.c opp = devfreq_recommended_opp(dev, &rate, 0); opp 272 drivers/devfreq/exynos-bus.c if (IS_ERR(opp)) { opp 274 drivers/devfreq/exynos-bus.c ret = PTR_ERR(opp); opp 277 drivers/devfreq/exynos-bus.c bus->curr_freq = dev_pm_opp_get_freq(opp); opp 278 drivers/devfreq/exynos-bus.c dev_pm_opp_put(opp); opp 22 drivers/devfreq/governor_passive.c struct dev_pm_opp *opp; opp 59 drivers/devfreq/governor_passive.c opp = devfreq_recommended_opp(parent_devfreq->dev.parent, freq, 0); opp 60 drivers/devfreq/governor_passive.c if (IS_ERR(opp)) { opp 61 drivers/devfreq/governor_passive.c ret = PTR_ERR(opp); opp 65 drivers/devfreq/governor_passive.c dev_pm_opp_put(opp); opp 78 drivers/devfreq/rk3399_dmc.c struct dev_pm_opp *opp; opp 85 drivers/devfreq/rk3399_dmc.c opp = devfreq_recommended_opp(dev, freq, flags); opp 86 drivers/devfreq/rk3399_dmc.c if (IS_ERR(opp)) opp 87 drivers/devfreq/rk3399_dmc.c return PTR_ERR(opp); opp 89 drivers/devfreq/rk3399_dmc.c target_rate = dev_pm_opp_get_freq(opp); opp 90 drivers/devfreq/rk3399_dmc.c target_volt = dev_pm_opp_get_voltage(opp); opp 91 drivers/devfreq/rk3399_dmc.c dev_pm_opp_put(opp); opp 314 drivers/devfreq/rk3399_dmc.c struct dev_pm_opp *opp; opp 438 drivers/devfreq/rk3399_dmc.c opp = devfreq_recommended_opp(dev, &data->rate, 0); opp 439 drivers/devfreq/rk3399_dmc.c if (IS_ERR(opp)) { opp 440 drivers/devfreq/rk3399_dmc.c ret = PTR_ERR(opp); opp 444 drivers/devfreq/rk3399_dmc.c data->rate = dev_pm_opp_get_freq(opp); opp 445 drivers/devfreq/rk3399_dmc.c data->volt = dev_pm_opp_get_voltage(opp); opp 446 drivers/devfreq/rk3399_dmc.c dev_pm_opp_put(opp); opp 42 drivers/devfreq/tegra20-devfreq.c struct dev_pm_opp *opp; opp 46 drivers/devfreq/tegra20-devfreq.c opp = devfreq_recommended_opp(dev, freq, flags); opp 47 drivers/devfreq/tegra20-devfreq.c if (IS_ERR(opp)) opp 48 drivers/devfreq/tegra20-devfreq.c return PTR_ERR(opp); opp 50 drivers/devfreq/tegra20-devfreq.c rate = dev_pm_opp_get_freq(opp); opp 51 drivers/devfreq/tegra20-devfreq.c dev_pm_opp_put(opp); opp 454 drivers/devfreq/tegra30-devfreq.c struct dev_pm_opp *opp; opp 458 drivers/devfreq/tegra30-devfreq.c opp = devfreq_recommended_opp(dev, freq, flags); opp 459 drivers/devfreq/tegra30-devfreq.c if (IS_ERR(opp)) { opp 461 drivers/devfreq/tegra30-devfreq.c return PTR_ERR(opp); opp 463 drivers/devfreq/tegra30-devfreq.c rate = dev_pm_opp_get_freq(opp); opp 464 drivers/devfreq/tegra30-devfreq.c dev_pm_opp_put(opp); opp 92 drivers/firmware/arm_scmi/perf.c } opp[0]; opp 143 drivers/firmware/arm_scmi/perf.c struct scmi_opp opp[MAX_OPPS]; opp 244 drivers/firmware/arm_scmi/perf.c struct scmi_opp *opp; opp 272 drivers/firmware/arm_scmi/perf.c opp = &perf_dom->opp[tot_opp_cnt]; opp 273 drivers/firmware/arm_scmi/perf.c for (cnt = 0; cnt < num_returned; cnt++, opp++) { opp 274 drivers/firmware/arm_scmi/perf.c opp->perf = le32_to_cpu(level_info->opp[cnt].perf_val); opp 275 drivers/firmware/arm_scmi/perf.c opp->power = le32_to_cpu(level_info->opp[cnt].power); opp 276 drivers/firmware/arm_scmi/perf.c opp->trans_latency_us = le16_to_cpu opp 277 drivers/firmware/arm_scmi/perf.c (level_info->opp[cnt].transition_latency_us); opp 280 drivers/firmware/arm_scmi/perf.c opp->perf, opp->power, opp->trans_latency_us); opp 293 drivers/firmware/arm_scmi/perf.c sort(perf_dom->opp, tot_opp_cnt, sizeof(*opp), opp_cmp_func, NULL); opp 600 drivers/firmware/arm_scmi/perf.c struct scmi_opp *opp; opp 610 drivers/firmware/arm_scmi/perf.c for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { opp 611 drivers/firmware/arm_scmi/perf.c freq = opp->perf * dom->mult_factor; opp 618 drivers/firmware/arm_scmi/perf.c freq = (--opp)->perf * dom->mult_factor; opp 639 drivers/firmware/arm_scmi/perf.c return dom->opp[dom->opp_count - 1].trans_latency_us * 1000; opp 674 drivers/firmware/arm_scmi/perf.c struct scmi_opp *opp; opp 680 drivers/firmware/arm_scmi/perf.c for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { opp 681 drivers/firmware/arm_scmi/perf.c opp_freq = opp->perf * dom->mult_factor; opp 686 drivers/firmware/arm_scmi/perf.c *power = opp->power; opp 613 drivers/firmware/arm_scpi.c struct scpi_opp *opp; opp 635 drivers/firmware/arm_scpi.c info->opps = kcalloc(info->count, sizeof(*opp), GFP_KERNEL); opp 641 drivers/firmware/arm_scpi.c for (i = 0, opp = info->opps; i < info->count; i++, opp++) { opp 642 drivers/firmware/arm_scpi.c opp->freq = le32_to_cpu(buf.opps[i].freq); opp 643 drivers/firmware/arm_scpi.c opp->m_volt = le32_to_cpu(buf.opps[i].m_volt); opp 646 drivers/firmware/arm_scpi.c sort(info->opps, info->count, sizeof(*opp), opp_cmp_func, NULL); opp 686 drivers/firmware/arm_scpi.c struct scpi_opp *opp; opp 695 drivers/firmware/arm_scpi.c for (opp = info->opps, idx = 0; idx < info->count; idx++, opp++) { opp 696 drivers/firmware/arm_scpi.c ret = dev_pm_opp_add(dev, opp->freq, opp->m_volt * 1000); opp 699 drivers/firmware/arm_scpi.c opp->freq, opp->m_volt); opp 701 drivers/firmware/arm_scpi.c dev_pm_opp_remove(dev, (--opp)->freq); opp 451 drivers/gpu/drm/amd/display/dc/core/dc.c pipes->stream_res.opp->funcs-> opp 452 drivers/gpu/drm/amd/display/dc/core/dc.c opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); opp 487 drivers/gpu/drm/amd/display/dc/core/dc.c pipes->stream_res.opp->inst); opp 1935 drivers/gpu/drm/amd/display/dc/core/dc.c pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp, opp 1940 drivers/gpu/drm/amd/display/dc/core/dc.c odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp, opp 3057 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; opp 3105 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms); opp 3110 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c else if (opp->funcs->opp_set_disp_pattern_generator) { opp 3120 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; opp 3130 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c opp->funcs->opp_set_disp_pattern_generator(opp, opp 3145 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c opp->funcs->opp_program_bit_depth_reduction(opp, ¶ms); opp 3151 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c else if (opp->funcs->opp_set_disp_pattern_generator) { opp 3160 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; opp 3170 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c opp->funcs->opp_set_disp_pattern_generator(opp, opp 408 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); opp 413 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); opp 1218 drivers/gpu/drm/amd/display/dc/core/dc_resource.c split_pipe->stream_res.opp = pool->opps[i]; opp 1291 drivers/gpu/drm/amd/display/dc/core/dc_resource.c free_pipe->stream_res.opp = tail_pipe->stream_res.opp; opp 1622 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.opp = pool->opps[i]; opp 1892 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->stream_res.opp = pool->opps[tg_inst]; opp 412 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct output_pixel_processor *opp, opp 415 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct dce110_opp *opp110 = TO_DCE110_OPP(opp); opp 423 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct output_pixel_processor *opp, opp 426 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct dce110_opp *opp110 = TO_DCE110_OPP(opp); opp 432 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c static void program_formatter_420_memory(struct output_pixel_processor *opp) opp 434 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct dce110_opp *opp110 = TO_DCE110_OPP(opp); opp 452 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct output_pixel_processor *opp, opp 457 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct dce110_opp *opp110 = TO_DCE110_OPP(opp); opp 491 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp) opp 493 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct dce110_opp *opp110 = TO_DCE110_OPP(opp); opp 505 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c struct output_pixel_processor *opp, opp 513 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c program_formatter_420_memory(opp); opp 516 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp, opp 520 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp, opp 524 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c program_formatter_reset_dig_resync_fifo(opp); opp 562 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c void dce110_opp_destroy(struct output_pixel_processor **opp) opp 564 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c if (*opp) opp 565 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c kfree(FROM_DCE11_OPP(*opp)); opp 566 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c *opp = NULL; opp 32 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define FROM_DCE11_OPP(opp)\ opp 33 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h container_of(opp, struct dce110_opp, base) opp 265 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define TO_DCE110_OPP(opp)\ opp 266 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h container_of(opp, struct dce110_opp, base) opp 282 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h void dce110_opp_destroy(struct output_pixel_processor **opp); opp 288 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h struct output_pixel_processor *opp, opp 292 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h struct output_pixel_processor *opp, opp 296 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h struct output_pixel_processor *opp, opp 302 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h struct output_pixel_processor *opp, opp 591 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c struct dce110_opp *opp = opp 594 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (!opp) opp 597 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce110_opp_construct(opp, opp 599 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &opp->base; opp 1390 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( opp 1391 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp, opp 1396 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_program_fmt( opp 1397 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream_res.opp, opp 1402 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( opp 1403 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c odm_pipe->stream_res.opp, opp 1408 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c odm_pipe->stream_res.opp->funcs->opp_program_fmt( opp 1409 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c odm_pipe->stream_res.opp, opp 637 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c struct dce110_opp *opp = opp 640 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!opp) opp 643 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_opp_construct(opp, opp 645 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &opp->base; opp 1065 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; opp 610 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c struct dce110_opp *opp = opp 613 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!opp) opp 616 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce110_opp_construct(opp, opp 618 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &opp->base; opp 385 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c struct dce110_opp *opp = opp 388 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (!opp) opp 391 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce110_opp_construct(opp, opp 393 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &opp->base; opp 471 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c struct dce110_opp *opp = opp 474 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!opp) opp 477 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce110_opp_construct(opp, opp 479 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &opp->base; opp 778 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_program_fmt( opp 779 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, opp 984 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; opp 986 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c mpc_tree_params = &(opp->mpc_tree_params); opp 994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (opp != NULL) opp 995 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; opp 1041 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) opp 1042 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( opp 1043 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, opp 1159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; opp 1845 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( opp 1846 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, opp 2191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); opp 2263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; opp 2378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->inst); opp 2858 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->funcs->opp_program_stereo( opp 2859 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp, opp 2894 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->stream_res.opp) opp 2898 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { opp 2902 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; opp 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct output_pixel_processor *opp, opp 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); opp 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct output_pixel_processor *opp, opp 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); opp 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct output_pixel_processor *opp, opp 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); opp 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct output_pixel_processor *opp, opp 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); opp 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c opp, opp 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c opp, opp 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct output_pixel_processor *opp, opp 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); opp 346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct output_pixel_processor *opp, opp 349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); opp 377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable) opp 379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); opp 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c void opp1_destroy(struct output_pixel_processor **opp) opp 391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c kfree(TO_DCN10_OPP(*opp)); opp 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c *opp = NULL; opp 30 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h #define TO_DCN10_OPP(opp)\ opp 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h container_of(opp, struct dcn10_opp, base) opp 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h struct output_pixel_processor *opp, opp 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h struct output_pixel_processor *opp, opp 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h struct output_pixel_processor *opp, opp 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h struct output_pixel_processor *opp, opp 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable); opp 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h void opp1_destroy(struct output_pixel_processor **opp); opp 620 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct dcn10_opp *opp = opp 623 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (!opp) { opp 628 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dcn10_opp_construct(opp, ctx, inst, opp 630 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &opp->base; opp 1108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c idle_pipe->stream_res.opp = head_pipe->stream_res.opp; opp 200 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct output_pixel_processor *opp = NULL; opp 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp = dc->res_pool->opps[opp_id_src0]; opp 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp->funcs->opp_set_disp_pattern_generator( opp 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp, opp 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_hwss_wait_for_blank_complete(opp); opp 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; opp 545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; opp 579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( opp 580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c odm_pipe->stream_res.opp, opp 583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( opp 584 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp, opp 595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp); opp 655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; opp 830 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; opp 833 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; opp 881 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c stream_res->opp->funcs->opp_set_disp_pattern_generator( opp 882 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c stream_res->opp, opp 890 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( opp 891 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c odm_pipe->stream_res.opp, opp 942 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( opp 943 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp, opp 1400 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct output_pixel_processor *opp) opp 1405 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (opp->funcs->dpg_is_blanked(opp)) opp 1732 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); opp 1799 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; opp 2070 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp = NULL; opp 2077 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; opp 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h struct output_pixel_processor *opp); opp 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c struct output_pixel_processor *opp, opp 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); opp 257 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c opp2_dpg_set_blank_color(opp, solid_color); opp 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c struct output_pixel_processor *opp, opp 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); opp 292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c bool opp2_dpg_is_blanked(struct output_pixel_processor *opp) opp 294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); opp 310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c struct output_pixel_processor *opp, opp 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); opp 30 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h #define TO_DCN20_OPP(opp)\ opp 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h container_of(opp, struct dcn20_opp, base) opp 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h struct output_pixel_processor *opp, opp 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h bool opp2_dpg_is_blanked(struct output_pixel_processor *opp); opp 151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h struct output_pixel_processor *opp, opp 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h struct output_pixel_processor *opp, opp 1011 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dcn20_opp *opp = opp 1014 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!opp) { opp 1019 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_opp_construct(opp, ctx, inst, opp 1021 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &opp->base; opp 1787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; opp 2951 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c idle_pipe->stream_res.opp = head_pipe->stream_res.opp; opp 1195 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dcn20_opp *opp = opp 1198 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!opp) { opp 1203 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_opp_construct(opp, ctx, inst, opp 1205 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &opp->base; opp 237 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct output_pixel_processor *opp; opp 276 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 281 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 287 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 292 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 296 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h void (*opp_destroy)(struct output_pixel_processor **opp); opp 299 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 304 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 309 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 317 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp); opp 320 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 324 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h struct output_pixel_processor *opp, opp 108 drivers/gpu/drm/msm/adreno/a5xx_power.c struct dev_pm_opp *opp; opp 111 drivers/gpu/drm/msm/adreno/a5xx_power.c opp = dev_pm_opp_find_freq_exact(&pdev->dev, freq, true); opp 113 drivers/gpu/drm/msm/adreno/a5xx_power.c if (!IS_ERR(opp)) { opp 114 drivers/gpu/drm/msm/adreno/a5xx_power.c ret = dev_pm_opp_get_voltage(opp) / 1000; opp 115 drivers/gpu/drm/msm/adreno/a5xx_power.c dev_pm_opp_put(opp); opp 996 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct dev_pm_opp *opp; opp 1002 drivers/gpu/drm/msm/adreno/a6xx_gmu.c opp = dev_pm_opp_find_freq_exact(dev, freq, true); opp 1003 drivers/gpu/drm/msm/adreno/a6xx_gmu.c if (IS_ERR(opp)) opp 1006 drivers/gpu/drm/msm/adreno/a6xx_gmu.c val = dev_pm_opp_get_level(opp); opp 1008 drivers/gpu/drm/msm/adreno/a6xx_gmu.c dev_pm_opp_put(opp); opp 1113 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct dev_pm_opp *opp; opp 1130 drivers/gpu/drm/msm/adreno/a6xx_gmu.c opp = dev_pm_opp_find_freq_ceil(dev, &freq); opp 1131 drivers/gpu/drm/msm/adreno/a6xx_gmu.c if (IS_ERR(opp)) opp 1134 drivers/gpu/drm/msm/adreno/a6xx_gmu.c dev_pm_opp_put(opp); opp 856 drivers/gpu/drm/msm/adreno/adreno_gpu.c struct dev_pm_opp *opp; opp 872 drivers/gpu/drm/msm/adreno/adreno_gpu.c opp = dev_pm_opp_find_freq_floor(dev, &freq); opp 873 drivers/gpu/drm/msm/adreno/adreno_gpu.c if (!IS_ERR(opp)) { opp 875 drivers/gpu/drm/msm/adreno/adreno_gpu.c dev_pm_opp_put(opp); opp 29 drivers/gpu/drm/msm/msm_gpu.c struct dev_pm_opp *opp; opp 31 drivers/gpu/drm/msm/msm_gpu.c opp = devfreq_recommended_opp(dev, freq, flags); opp 33 drivers/gpu/drm/msm/msm_gpu.c if (IS_ERR(opp)) opp 34 drivers/gpu/drm/msm/msm_gpu.c return PTR_ERR(opp); opp 41 drivers/gpu/drm/msm/msm_gpu.c dev_pm_opp_put(opp); opp 22 drivers/gpu/drm/panfrost/panfrost_devfreq.c struct dev_pm_opp *opp; opp 27 drivers/gpu/drm/panfrost/panfrost_devfreq.c opp = devfreq_recommended_opp(dev, freq, flags); opp 28 drivers/gpu/drm/panfrost/panfrost_devfreq.c if (IS_ERR(opp)) opp 29 drivers/gpu/drm/panfrost/panfrost_devfreq.c return PTR_ERR(opp); opp 31 drivers/gpu/drm/panfrost/panfrost_devfreq.c target_rate = dev_pm_opp_get_freq(opp); opp 32 drivers/gpu/drm/panfrost/panfrost_devfreq.c target_volt = dev_pm_opp_get_voltage(opp); opp 33 drivers/gpu/drm/panfrost/panfrost_devfreq.c dev_pm_opp_put(opp); opp 139 drivers/gpu/drm/panfrost/panfrost_devfreq.c struct dev_pm_opp *opp; opp 151 drivers/gpu/drm/panfrost/panfrost_devfreq.c opp = devfreq_recommended_opp(&pfdev->pdev->dev, &pfdev->devfreq.cur_freq, 0); opp 152 drivers/gpu/drm/panfrost/panfrost_devfreq.c if (IS_ERR(opp)) opp 153 drivers/gpu/drm/panfrost/panfrost_devfreq.c return PTR_ERR(opp); opp 156 drivers/gpu/drm/panfrost/panfrost_devfreq.c dev_pm_opp_put(opp); opp 891 drivers/mfd/db8500-prcmu.c int db8500_prcmu_set_arm_opp(u8 opp) opp 895 drivers/mfd/db8500-prcmu.c if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) opp 906 drivers/mfd/db8500-prcmu.c writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); opp 913 drivers/mfd/db8500-prcmu.c (mb1_transfer.ack.arm_opp != opp)) opp 994 drivers/mfd/db8500-prcmu.c int db8500_prcmu_set_ape_opp(u8 opp) opp 998 drivers/mfd/db8500-prcmu.c if (opp == mb1_transfer.ape_opp) opp 1006 drivers/mfd/db8500-prcmu.c if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) opp 1014 drivers/mfd/db8500-prcmu.c writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), opp 1021 drivers/mfd/db8500-prcmu.c (mb1_transfer.ack.ape_opp != opp)) opp 1025 drivers/mfd/db8500-prcmu.c if ((!r && (opp == APE_50_PARTLY_25_OPP)) || opp 1029 drivers/mfd/db8500-prcmu.c mb1_transfer.ape_opp = opp; opp 101 drivers/opp/core.c unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp) opp 103 drivers/opp/core.c if (IS_ERR_OR_NULL(opp)) { opp 108 drivers/opp/core.c return opp->supplies[0].u_volt; opp 119 drivers/opp/core.c unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp) opp 121 drivers/opp/core.c if (IS_ERR_OR_NULL(opp) || !opp->available) { opp 126 drivers/opp/core.c return opp->rate; opp 137 drivers/opp/core.c unsigned int dev_pm_opp_get_level(struct dev_pm_opp *opp) opp 139 drivers/opp/core.c if (IS_ERR_OR_NULL(opp) || !opp->available) { opp 144 drivers/opp/core.c return opp->level; opp 158 drivers/opp/core.c bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp) opp 160 drivers/opp/core.c if (IS_ERR_OR_NULL(opp) || !opp->available) { opp 165 drivers/opp/core.c return opp->turbo; opp 201 drivers/opp/core.c struct dev_pm_opp *opp; opp 230 drivers/opp/core.c list_for_each_entry(opp, &opp_table->opp_list, node) { opp 231 drivers/opp/core.c if (!opp->available) opp 234 drivers/opp/core.c if (opp->supplies[i].u_volt_min < uV[i].min) opp 235 drivers/opp/core.c uV[i].min = opp->supplies[i].u_volt_min; opp 236 drivers/opp/core.c if (opp->supplies[i].u_volt_max > uV[i].max) opp 237 drivers/opp/core.c uV[i].max = opp->supplies[i].u_volt_max; opp 304 drivers/opp/core.c struct dev_pm_opp *opp; opp 309 drivers/opp/core.c list_for_each_entry(opp, &opp_table->opp_list, node) { opp 310 drivers/opp/core.c if (opp->available) opp 374 drivers/opp/core.c struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp 389 drivers/opp/core.c opp = temp_opp; opp 392 drivers/opp/core.c dev_pm_opp_get(opp); opp 400 drivers/opp/core.c return opp; opp 423 drivers/opp/core.c struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp 437 drivers/opp/core.c opp = temp_opp; opp 440 drivers/opp/core.c dev_pm_opp_get(opp); opp 448 drivers/opp/core.c return opp; opp 455 drivers/opp/core.c struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp 461 drivers/opp/core.c opp = temp_opp; opp 462 drivers/opp/core.c *freq = opp->rate; opp 465 drivers/opp/core.c dev_pm_opp_get(opp); opp 472 drivers/opp/core.c return opp; opp 497 drivers/opp/core.c struct dev_pm_opp *opp; opp 508 drivers/opp/core.c opp = _find_freq_ceil(opp_table, freq); opp 512 drivers/opp/core.c return opp; opp 538 drivers/opp/core.c struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp 557 drivers/opp/core.c opp = temp_opp; opp 562 drivers/opp/core.c if (!IS_ERR(opp)) opp 563 drivers/opp/core.c dev_pm_opp_get(opp); opp 567 drivers/opp/core.c if (!IS_ERR(opp)) opp 568 drivers/opp/core.c *freq = opp->rate; opp 570 drivers/opp/core.c return opp; opp 595 drivers/opp/core.c struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp 613 drivers/opp/core.c opp = temp_opp; opp 618 drivers/opp/core.c if (!IS_ERR(opp)) opp 619 drivers/opp/core.c dev_pm_opp_get(opp); opp 624 drivers/opp/core.c return opp; opp 747 drivers/opp/core.c struct dev_pm_opp *opp) opp 759 drivers/opp/core.c pstate = likely(opp) ? opp->required_opps[0]->pstate : 0; opp 777 drivers/opp/core.c pstate = likely(opp) ? opp->required_opps[i]->pstate : 0; opp 809 drivers/opp/core.c struct dev_pm_opp *old_opp, *opp; opp 860 drivers/opp/core.c opp = _find_freq_ceil(opp_table, &temp_freq); opp 861 drivers/opp/core.c if (IS_ERR(opp)) { opp 862 drivers/opp/core.c ret = PTR_ERR(opp); opp 873 drivers/opp/core.c ret = _set_required_opps(dev, opp_table, opp); opp 881 drivers/opp/core.c opp->supplies); opp 885 drivers/opp/core.c opp->supplies); opp 893 drivers/opp/core.c ret = _set_required_opps(dev, opp_table, opp); opp 899 drivers/opp/core.c dev_pm_opp_put(opp); opp 1077 drivers/opp/core.c struct dev_pm_opp *opp, *tmp; opp 1079 drivers/opp/core.c list_for_each_entry_safe(opp, tmp, &opp_table->opp_list, node) { opp 1080 drivers/opp/core.c if (!opp->dynamic) opp 1081 drivers/opp/core.c dev_pm_opp_put(opp); opp 1109 drivers/opp/core.c void _opp_free(struct dev_pm_opp *opp) opp 1111 drivers/opp/core.c kfree(opp); opp 1114 drivers/opp/core.c static void _opp_kref_release(struct dev_pm_opp *opp, opp 1121 drivers/opp/core.c blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_REMOVE, opp); opp 1122 drivers/opp/core.c _of_opp_free_required_opps(opp_table, opp); opp 1123 drivers/opp/core.c opp_debug_remove_one(opp); opp 1124 drivers/opp/core.c list_del(&opp->node); opp 1125 drivers/opp/core.c kfree(opp); opp 1130 drivers/opp/core.c struct dev_pm_opp *opp = container_of(kref, struct dev_pm_opp, kref); opp 1131 drivers/opp/core.c struct opp_table *opp_table = opp->opp_table; opp 1133 drivers/opp/core.c _opp_kref_release(opp, opp_table); opp 1138 drivers/opp/core.c struct dev_pm_opp *opp = container_of(kref, struct dev_pm_opp, kref); opp 1139 drivers/opp/core.c struct opp_table *opp_table = opp->opp_table; opp 1141 drivers/opp/core.c _opp_kref_release(opp, opp_table); opp 1145 drivers/opp/core.c void dev_pm_opp_get(struct dev_pm_opp *opp) opp 1147 drivers/opp/core.c kref_get(&opp->kref); opp 1150 drivers/opp/core.c void dev_pm_opp_put(struct dev_pm_opp *opp) opp 1152 drivers/opp/core.c kref_put_mutex(&opp->kref, _opp_kref_release_locked, opp 1153 drivers/opp/core.c &opp->opp_table->lock); opp 1157 drivers/opp/core.c static void dev_pm_opp_put_unlocked(struct dev_pm_opp *opp) opp 1159 drivers/opp/core.c kref_put(&opp->kref, _opp_kref_release_unlocked); opp 1171 drivers/opp/core.c struct dev_pm_opp *opp; opp 1181 drivers/opp/core.c list_for_each_entry(opp, &opp_table->opp_list, node) { opp 1182 drivers/opp/core.c if (opp->rate == freq) { opp 1191 drivers/opp/core.c dev_pm_opp_put(opp); opp 1214 drivers/opp/core.c struct dev_pm_opp *opp, *temp; opp 1222 drivers/opp/core.c list_for_each_entry_safe(opp, temp, &opp_table->opp_list, node) { opp 1223 drivers/opp/core.c if (opp->dynamic) { opp 1224 drivers/opp/core.c dev_pm_opp_put_unlocked(opp); opp 1241 drivers/opp/core.c struct dev_pm_opp *opp; opp 1246 drivers/opp/core.c supply_size = sizeof(*opp->supplies) * count; opp 1249 drivers/opp/core.c opp = kzalloc(sizeof(*opp) + supply_size, GFP_KERNEL); opp 1250 drivers/opp/core.c if (!opp) opp 1254 drivers/opp/core.c opp->supplies = (struct dev_pm_opp_supply *)(opp + 1); opp 1255 drivers/opp/core.c INIT_LIST_HEAD(&opp->node); opp 1257 drivers/opp/core.c return opp; opp 1260 drivers/opp/core.c static bool _opp_supported_by_regulators(struct dev_pm_opp *opp, opp 1273 drivers/opp/core.c opp->supplies[i].u_volt_min, opp 1274 drivers/opp/core.c opp->supplies[i].u_volt_max)) { opp 1276 drivers/opp/core.c __func__, opp->supplies[i].u_volt_min, opp 1277 drivers/opp/core.c opp->supplies[i].u_volt_max); opp 1289 drivers/opp/core.c struct dev_pm_opp *opp; opp 1299 drivers/opp/core.c list_for_each_entry(opp, &opp_table->opp_list, node) { opp 1300 drivers/opp/core.c if (new_opp->rate > opp->rate) { opp 1301 drivers/opp/core.c *head = &opp->node; opp 1305 drivers/opp/core.c if (new_opp->rate < opp->rate) opp 1310 drivers/opp/core.c __func__, opp->rate, opp->supplies[0].u_volt, opp 1311 drivers/opp/core.c opp->available, new_opp->rate, opp 1315 drivers/opp/core.c return opp->available && opp 1316 drivers/opp/core.c new_opp->supplies[0].u_volt == opp->supplies[0].u_volt ? -EBUSY : -EEXIST; opp 1952 drivers/opp/core.c struct dev_pm_opp *opp; opp 1982 drivers/opp/core.c list_for_each_entry(opp, &src_table->opp_list, node) { opp 1983 drivers/opp/core.c if (opp->pstate == pstate) { opp 1984 drivers/opp/core.c dest_pstate = opp->required_opps[i]->pstate; opp 2052 drivers/opp/core.c struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV); opp 2068 drivers/opp/core.c opp = tmp_opp; opp 2073 drivers/opp/core.c if (IS_ERR(opp)) { opp 2074 drivers/opp/core.c r = PTR_ERR(opp); opp 2079 drivers/opp/core.c if (opp->available == availability_req) opp 2082 drivers/opp/core.c opp->available = availability_req; opp 2084 drivers/opp/core.c dev_pm_opp_get(opp); opp 2090 drivers/opp/core.c opp); opp 2093 drivers/opp/core.c OPP_EVENT_DISABLE, opp); opp 2095 drivers/opp/core.c dev_pm_opp_put(opp); opp 46 drivers/opp/cpu.c struct dev_pm_opp *opp; opp 61 drivers/opp/cpu.c opp = dev_pm_opp_find_freq_ceil(dev, &rate); opp 62 drivers/opp/cpu.c if (IS_ERR(opp)) { opp 63 drivers/opp/cpu.c ret = PTR_ERR(opp); opp 70 drivers/opp/cpu.c if (dev_pm_opp_is_turbo(opp)) opp 73 drivers/opp/cpu.c dev_pm_opp_put(opp); opp 30 drivers/opp/debugfs.c void opp_debug_remove_one(struct dev_pm_opp *opp) opp 32 drivers/opp/debugfs.c debugfs_remove_recursive(opp->dentry); opp 35 drivers/opp/debugfs.c static void opp_debug_create_supplies(struct dev_pm_opp *opp, opp 51 drivers/opp/debugfs.c &opp->supplies[i].u_volt); opp 54 drivers/opp/debugfs.c &opp->supplies[i].u_volt_min); opp 57 drivers/opp/debugfs.c &opp->supplies[i].u_volt_max); opp 60 drivers/opp/debugfs.c &opp->supplies[i].u_amp); opp 64 drivers/opp/debugfs.c void opp_debug_create_one(struct dev_pm_opp *opp, struct opp_table *opp_table) opp 77 drivers/opp/debugfs.c if (likely(opp->rate)) opp 78 drivers/opp/debugfs.c id = opp->rate; opp 87 drivers/opp/debugfs.c debugfs_create_bool("available", S_IRUGO, d, &opp->available); opp 88 drivers/opp/debugfs.c debugfs_create_bool("dynamic", S_IRUGO, d, &opp->dynamic); opp 89 drivers/opp/debugfs.c debugfs_create_bool("turbo", S_IRUGO, d, &opp->turbo); opp 90 drivers/opp/debugfs.c debugfs_create_bool("suspend", S_IRUGO, d, &opp->suspend); opp 91 drivers/opp/debugfs.c debugfs_create_u32("performance_state", S_IRUGO, d, &opp->pstate); opp 92 drivers/opp/debugfs.c debugfs_create_ulong("rate_hz", S_IRUGO, d, &opp->rate); opp 94 drivers/opp/debugfs.c &opp->clock_latency_ns); opp 96 drivers/opp/debugfs.c opp_debug_create_supplies(opp, opp_table, d); opp 98 drivers/opp/debugfs.c opp->dentry = d; opp 78 drivers/opp/of.c struct dev_pm_opp *opp; opp 82 drivers/opp/of.c list_for_each_entry(opp, &opp_table->opp_list, node) { opp 83 drivers/opp/of.c if (opp->np == opp_np) { opp 84 drivers/opp/of.c dev_pm_opp_get(opp); opp 86 drivers/opp/of.c return opp; opp 269 drivers/opp/of.c struct dev_pm_opp *opp) opp 271 drivers/opp/of.c struct dev_pm_opp **required_opps = opp->required_opps; opp 286 drivers/opp/of.c opp->required_opps = NULL; opp 291 drivers/opp/of.c struct dev_pm_opp *opp) opp 305 drivers/opp/of.c opp->required_opps = required_opps; opp 310 drivers/opp/of.c np = of_parse_required_opp(opp->np, i); opp 321 drivers/opp/of.c __func__, opp->np, i); opp 330 drivers/opp/of.c _of_opp_free_required_opps(opp_table, opp); opp 372 drivers/opp/of.c static int opp_parse_supplies(struct dev_pm_opp *opp, struct device *dev, opp 384 drivers/opp/of.c prop = of_find_property(opp->np, name, NULL); opp 390 drivers/opp/of.c prop = of_find_property(opp->np, name, NULL); opp 417 drivers/opp/of.c vcount = of_property_count_u32_elems(opp->np, name); opp 435 drivers/opp/of.c ret = of_property_read_u32_array(opp->np, name, microvolt, vcount); opp 447 drivers/opp/of.c prop = of_find_property(opp->np, name, NULL); opp 453 drivers/opp/of.c prop = of_find_property(opp->np, name, NULL); opp 457 drivers/opp/of.c icount = of_property_count_u32_elems(opp->np, name); opp 478 drivers/opp/of.c ret = of_property_read_u32_array(opp->np, name, microamp, opp 489 drivers/opp/of.c opp->supplies[i].u_volt = microvolt[j++]; opp 492 drivers/opp/of.c opp->supplies[i].u_volt_min = opp->supplies[i].u_volt; opp 493 drivers/opp/of.c opp->supplies[i].u_volt_max = opp->supplies[i].u_volt; opp 495 drivers/opp/of.c opp->supplies[i].u_volt_min = microvolt[j++]; opp 496 drivers/opp/of.c opp->supplies[i].u_volt_max = microvolt[j++]; opp 500 drivers/opp/of.c opp->supplies[i].u_amp = microamp[i]; opp 658 drivers/opp/of.c struct dev_pm_opp *opp; opp 675 drivers/opp/of.c opp = _opp_add_static_v2(opp_table, dev, np); opp 676 drivers/opp/of.c if (IS_ERR(opp)) { opp 677 drivers/opp/of.c ret = PTR_ERR(opp); opp 682 drivers/opp/of.c } else if (opp) { opp 693 drivers/opp/of.c list_for_each_entry(opp, &opp_table->opp_list, node) opp 694 drivers/opp/of.c pstate_count += !!opp->pstate; opp 991 drivers/opp/of.c struct dev_pm_opp *opp; opp 1007 drivers/opp/of.c opp = _find_opp_of_np(opp_table, required_np); opp 1008 drivers/opp/of.c if (opp) { opp 1009 drivers/opp/of.c pstate = opp->pstate; opp 1010 drivers/opp/of.c dev_pm_opp_put(opp); opp 1030 drivers/opp/of.c struct device_node *dev_pm_opp_get_of_node(struct dev_pm_opp *opp) opp 1032 drivers/opp/of.c if (IS_ERR_OR_NULL(opp)) { opp 1037 drivers/opp/of.c return of_node_get(opp->np); opp 1057 drivers/opp/of.c struct dev_pm_opp *opp; opp 1078 drivers/opp/of.c opp = dev_pm_opp_find_freq_ceil(cpu_dev, &Hz); opp 1079 drivers/opp/of.c if (IS_ERR(opp)) opp 1082 drivers/opp/of.c mV = dev_pm_opp_get_voltage(opp) / 1000; opp 1083 drivers/opp/of.c dev_pm_opp_put(opp); opp 207 drivers/opp/opp.h void dev_pm_opp_get(struct dev_pm_opp *opp); opp 215 drivers/opp/opp.h void _opp_free(struct dev_pm_opp *opp); opp 227 drivers/opp/opp.h struct dev_pm_opp *opp); opp 233 drivers/opp/opp.h struct dev_pm_opp *opp) {} opp 237 drivers/opp/opp.h void opp_debug_remove_one(struct dev_pm_opp *opp); opp 238 drivers/opp/opp.h void opp_debug_create_one(struct dev_pm_opp *opp, struct opp_table *opp_table); opp 242 drivers/opp/opp.h static inline void opp_debug_remove_one(struct dev_pm_opp *opp) {} opp 244 drivers/opp/opp.h static inline void opp_debug_create_one(struct dev_pm_opp *opp, opp 123 drivers/sbus/char/openprom.c static int copyout(void __user *info, struct openpromio *opp, int len) opp 125 drivers/sbus/char/openprom.c if (copy_to_user(info, opp, len)) opp 294 drivers/sbus/char/openprom.c struct openpromio *opp = NULL; opp 300 drivers/sbus/char/openprom.c bufsize = getstrings(argp, &opp); opp 302 drivers/sbus/char/openprom.c bufsize = copyin(argp, &opp); opp 312 drivers/sbus/char/openprom.c error = opromgetprop(argp, dp, opp, bufsize); opp 317 drivers/sbus/char/openprom.c error = opromnxtprop(argp, dp, opp, bufsize); opp 322 drivers/sbus/char/openprom.c error = opromsetopt(dp, opp, bufsize); opp 328 drivers/sbus/char/openprom.c error = opromnext(argp, cmd, dp, opp, bufsize, data); opp 332 drivers/sbus/char/openprom.c error = oprompci2node(argp, dp, opp, bufsize, data); opp 336 drivers/sbus/char/openprom.c error = oprompath2node(argp, dp, opp, bufsize, data); opp 340 drivers/sbus/char/openprom.c error = opromgetbootargs(argp, opp, bufsize); opp 357 drivers/sbus/char/openprom.c kfree(opp); opp 285 drivers/soc/qcom/rpmhpd.c struct dev_pm_opp *opp) opp 287 drivers/soc/qcom/rpmhpd.c return dev_pm_opp_get_level(opp); opp 332 drivers/soc/qcom/rpmpd.c struct dev_pm_opp *opp) opp 334 drivers/soc/qcom/rpmpd.c return dev_pm_opp_get_level(opp); opp 137 drivers/thermal/cpu_cooling.c struct dev_pm_opp *opp; opp 170 drivers/thermal/cpu_cooling.c opp = dev_pm_opp_find_freq_ceil(dev, &freq); opp 171 drivers/thermal/cpu_cooling.c if (IS_ERR(opp)) { opp 177 drivers/thermal/cpu_cooling.c voltage_mv = dev_pm_opp_get_voltage(opp) / 1000; opp 178 drivers/thermal/cpu_cooling.c dev_pm_opp_put(opp); opp 85 drivers/thermal/devfreq_cooling.c struct dev_pm_opp *opp; opp 90 drivers/thermal/devfreq_cooling.c opp = dev_pm_opp_find_freq_exact(dev, freq, !want_enable); opp 92 drivers/thermal/devfreq_cooling.c if (PTR_ERR(opp) == -ERANGE) opp 94 drivers/thermal/devfreq_cooling.c else if (IS_ERR(opp)) opp 95 drivers/thermal/devfreq_cooling.c return PTR_ERR(opp); opp 97 drivers/thermal/devfreq_cooling.c dev_pm_opp_put(opp); opp 181 drivers/thermal/devfreq_cooling.c struct dev_pm_opp *opp; opp 183 drivers/thermal/devfreq_cooling.c opp = dev_pm_opp_find_freq_exact(dev, freq, true); opp 184 drivers/thermal/devfreq_cooling.c if (PTR_ERR(opp) == -ERANGE) opp 185 drivers/thermal/devfreq_cooling.c opp = dev_pm_opp_find_freq_exact(dev, freq, false); opp 187 drivers/thermal/devfreq_cooling.c if (IS_ERR(opp)) { opp 189 drivers/thermal/devfreq_cooling.c freq, PTR_ERR(opp)); opp 193 drivers/thermal/devfreq_cooling.c voltage = dev_pm_opp_get_voltage(opp) / 1000; /* mV */ opp 194 drivers/thermal/devfreq_cooling.c dev_pm_opp_put(opp); opp 447 drivers/thermal/devfreq_cooling.c struct dev_pm_opp *opp; opp 449 drivers/thermal/devfreq_cooling.c opp = dev_pm_opp_find_freq_floor(dev, &freq); opp 450 drivers/thermal/devfreq_cooling.c if (IS_ERR(opp)) { opp 451 drivers/thermal/devfreq_cooling.c ret = PTR_ERR(opp); opp 455 drivers/thermal/devfreq_cooling.c voltage = dev_pm_opp_get_voltage(opp) / 1000; /* mV */ opp 456 drivers/thermal/devfreq_cooling.c dev_pm_opp_put(opp); opp 536 include/linux/mfd/db8500-prcmu.h int db8500_prcmu_set_arm_opp(u8 opp); opp 538 include/linux/mfd/db8500-prcmu.h int db8500_prcmu_set_ape_opp(u8 opp); opp 576 include/linux/mfd/db8500-prcmu.h static inline int db8500_prcmu_set_ape_opp(u8 opp) opp 744 include/linux/mfd/db8500-prcmu.h static inline int db8500_prcmu_set_arm_opp(u8 opp) opp 276 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_set_arm_opp(u8 opp) opp 278 include/linux/mfd/dbx500-prcmu.h return db8500_prcmu_set_arm_opp(opp); opp 286 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_set_ape_opp(u8 opp) opp 288 include/linux/mfd/dbx500-prcmu.h return db8500_prcmu_set_ape_opp(opp); opp 462 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_set_ape_opp(u8 opp) opp 477 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_set_arm_opp(u8 opp) opp 117 include/linux/pm_domain.h struct dev_pm_opp *opp); opp 291 include/linux/pm_domain.h struct dev_pm_opp *opp); opp 333 include/linux/pm_domain.h struct dev_pm_opp *opp) opp 82 include/linux/pm_opp.h unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp); opp 84 include/linux/pm_opp.h unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp); opp 86 include/linux/pm_opp.h unsigned int dev_pm_opp_get_level(struct dev_pm_opp *opp); opp 88 include/linux/pm_opp.h bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp); opp 109 include/linux/pm_opp.h void dev_pm_opp_put(struct dev_pm_opp *opp); opp 154 include/linux/pm_opp.h static inline unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp) opp 159 include/linux/pm_opp.h static inline unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp) opp 164 include/linux/pm_opp.h static inline unsigned int dev_pm_opp_get_level(struct dev_pm_opp *opp) opp 169 include/linux/pm_opp.h static inline bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp) opp 229 include/linux/pm_opp.h static inline void dev_pm_opp_put(struct dev_pm_opp *opp) {} opp 348 include/linux/pm_opp.h struct device_node *dev_pm_opp_get_of_node(struct dev_pm_opp *opp); opp 385 include/linux/pm_opp.h static inline struct device_node *dev_pm_opp_get_of_node(struct dev_pm_opp *opp)