op_inst          1803 arch/mips/kvm/emulate.c 	u32 cache, op_inst, op, base;
op_inst          1819 arch/mips/kvm/emulate.c 	op_inst = inst.i_format.rt;
op_inst          1824 arch/mips/kvm/emulate.c 	cache = op_inst & CacheOp_Cache;
op_inst          1825 arch/mips/kvm/emulate.c 	op = op_inst & CacheOp_Op;
op_inst          1883 arch/mips/kvm/emulate.c 	if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
op_inst          1899 arch/mips/kvm/emulate.c 	} else if (op_inst == Hit_Invalidate_I) {
op_inst          1069 arch/mips/kvm/vz.c 	u32 cache, op_inst, op, base;
op_inst          1084 arch/mips/kvm/vz.c 	op_inst = inst.i_format.rt;
op_inst          1089 arch/mips/kvm/vz.c 	cache = op_inst & CacheOp_Cache;
op_inst          1090 arch/mips/kvm/vz.c 	op = op_inst & CacheOp_Op;
op_inst          1101 arch/mips/kvm/vz.c 	switch (op_inst) {