offset_max         91 arch/x86/events/amd/ibs.c 	int				offset_max;
offset_max        538 arch/x86/events/amd/ibs.c 	.offset_max		= MSR_AMD64_IBSFETCH_REG_COUNT,
offset_max        563 arch/x86/events/amd/ibs.c 	.offset_max		= MSR_AMD64_IBSOP_REG_COUNT,
offset_max        578 arch/x86/events/amd/ibs.c 	int offset, size, check_rip, offset_max, throttle = 0;
offset_max        617 arch/x86/events/amd/ibs.c 		offset_max = perf_ibs->offset_max;
offset_max        619 arch/x86/events/amd/ibs.c 		offset_max = 3;
offset_max        621 arch/x86/events/amd/ibs.c 		offset_max = 1;
offset_max        626 arch/x86/events/amd/ibs.c 				       perf_ibs->offset_max,
offset_max        628 arch/x86/events/amd/ibs.c 	} while (offset < offset_max);
offset_max        113 drivers/gpu/drm/radeon/mkregtable.c 	unsigned offset_max;
offset_max        139 drivers/gpu/drm/radeon/mkregtable.c 	t->offset_max = 0;
offset_max        174 drivers/gpu/drm/radeon/mkregtable.c 	t->nentry = ((t->offset_max >> 2) + 31) / 32;
offset_max        254 drivers/gpu/drm/radeon/mkregtable.c 				if (o > t->offset_max)
offset_max        255 drivers/gpu/drm/radeon/mkregtable.c 					t->offset_max = o;
offset_max        260 drivers/gpu/drm/radeon/mkregtable.c 	if (t->offset_max < last_reg)
offset_max        261 drivers/gpu/drm/radeon/mkregtable.c 		t->offset_max = last_reg;
offset_max       8339 drivers/scsi/ncr53c8xx.c 	np->maxoffs	= device->chip.offset_max;
offset_max        461 drivers/scsi/ncr53c8xx.h 	unsigned char	offset_max;
offset_max         41 drivers/scsi/sym53c8xx_2/sym_defs.h 	u_char	offset_max;
offset_max       1287 drivers/scsi/sym53c8xx_2/sym_glue.c 	np->maxoffs	= dev->chip.offset_max;
offset_max         43 drivers/scsi/zalon.c 	.offset_max =	8,