offset_mask        90 arch/x86/events/amd/ibs.c 	unsigned long			offset_mask[1];
offset_mask       537 arch/x86/events/amd/ibs.c 	.offset_mask		= { MSR_AMD64_IBSFETCH_REG_MASK },
offset_mask       562 arch/x86/events/amd/ibs.c 	.offset_mask		= { MSR_AMD64_IBSOP_REG_MASK },
offset_mask       625 arch/x86/events/amd/ibs.c 		offset = find_next_bit(perf_ibs->offset_mask,
offset_mask       166 drivers/gpio/gpio-pcie-idio-24.c 	const unsigned long offset_mask = BIT(offset % 8);
offset_mask       171 drivers/gpio/gpio-pcie-idio-24.c 		return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask);
offset_mask       174 drivers/gpio/gpio-pcie-idio-24.c 		return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask);
offset_mask       177 drivers/gpio/gpio-pcie-idio-24.c 		return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask);
offset_mask       181 drivers/gpio/gpio-pcie-idio-24.c 		return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask);
offset_mask       184 drivers/gpio/gpio-pcie-idio-24.c 		return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask);
offset_mask       187 drivers/gpio/gpio-pcie-idio-24.c 		return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask);
offset_mask       191 drivers/gpio/gpio-pcie-idio-24.c 		return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask);
offset_mask       194 drivers/gpio/gpio-pcie-idio-24.c 	return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask);
offset_mask      1813 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 		info->offset_mask = info->offset - 1;
offset_mask       546 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 		info->offset_mask = info->offset - 1;
offset_mask       358 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c 		info->offset_mask = info->offset - 1;
offset_mask       380 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c 		info->offset_mask = info->offset - 1;
offset_mask       392 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c 		info->offset_mask = info->offset - 1;
offset_mask       380 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c 		info->offset_mask = info->offset - 1;
offset_mask       351 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c 		info->offset_mask = info->offset - 1;
offset_mask       354 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c 		info->offset_mask = info->offset - 1;
offset_mask        80 drivers/gpu/drm/amd/display/include/gpio_types.h 	uint32_t offset_mask;
offset_mask      3143 drivers/iommu/amd_iommu.c 	unsigned long offset_mask, pte_pgsize;
offset_mask      3154 drivers/iommu/amd_iommu.c 	offset_mask = pte_pgsize - 1;
offset_mask      3157 drivers/iommu/amd_iommu.c 	return (__pte & ~offset_mask) | (iova & offset_mask);
offset_mask       538 drivers/misc/habanalabs/debugfs.c 	u64 offset_mask = HOP4_MASK | OFFSET_MASK;
offset_mask       582 drivers/misc/habanalabs/debugfs.c 		offset_mask = OFFSET_MASK;
offset_mask       588 drivers/misc/habanalabs/debugfs.c 	*phys_addr = (hop_pte & ~offset_mask) | (virt_addr & offset_mask);
offset_mask      1045 drivers/mmc/host/sdhci.c 		unsigned int length_mask, offset_mask;
offset_mask      1058 drivers/mmc/host/sdhci.c 		offset_mask = 0;
offset_mask      1067 drivers/mmc/host/sdhci.c 				offset_mask = 3;
offset_mask      1073 drivers/mmc/host/sdhci.c 				offset_mask = 3;
offset_mask      1076 drivers/mmc/host/sdhci.c 		if (unlikely(length_mask | offset_mask)) {
offset_mask      1084 drivers/mmc/host/sdhci.c 				if (sg->offset & offset_mask) {
offset_mask       152 drivers/soc/mediatek/mtk-cmdq-helper.c 	u32 offset_mask = offset;
offset_mask       157 drivers/soc/mediatek/mtk-cmdq-helper.c 		offset_mask |= CMDQ_WRITE_ENABLE_MASK;
offset_mask       159 drivers/soc/mediatek/mtk-cmdq-helper.c 	err |= cmdq_pkt_write(pkt, subsys, offset_mask, value);