PIXEL_RATE_CNTL   919 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
PIXEL_RATE_CNTL    73 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 0),\
PIXEL_RATE_CNTL    74 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 1),\
PIXEL_RATE_CNTL    75 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 2),\
PIXEL_RATE_CNTL    76 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 3),\
PIXEL_RATE_CNTL    77 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 4),\
PIXEL_RATE_CNTL    78 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 5)
PIXEL_RATE_CNTL    92 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 0),\
PIXEL_RATE_CNTL    93 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 1),\
PIXEL_RATE_CNTL    94 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 2),\
PIXEL_RATE_CNTL    95 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 3)
PIXEL_RATE_CNTL   118 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 0), \
PIXEL_RATE_CNTL   119 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 1), \
PIXEL_RATE_CNTL   120 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 2), \
PIXEL_RATE_CNTL   121 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PIXEL_RATE_CNTL, OTG, 3)
PIXEL_RATE_CNTL   160 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
PIXEL_RATE_CNTL   171 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
PIXEL_RATE_CNTL   181 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
PIXEL_RATE_CNTL   187 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 		REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
PIXEL_RATE_CNTL    66 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SRII(PIXEL_RATE_CNTL, blk, inst), \
PIXEL_RATE_CNTL    70 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SRII(PIXEL_RATE_CNTL, blk, 0), \
PIXEL_RATE_CNTL    71 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SRII(PIXEL_RATE_CNTL, blk, 1), \
PIXEL_RATE_CNTL    72 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SRII(PIXEL_RATE_CNTL, blk, 2), \
PIXEL_RATE_CNTL    73 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SRII(PIXEL_RATE_CNTL, blk, 3), \
PIXEL_RATE_CNTL    74 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SRII(PIXEL_RATE_CNTL, blk, 4), \
PIXEL_RATE_CNTL    75 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SRII(PIXEL_RATE_CNTL, blk, 5)
PIXEL_RATE_CNTL   347 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t PIXEL_RATE_CNTL[6];
PIXEL_RATE_CNTL   465 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
PIXEL_RATE_CNTL   466 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)