PIXCLK_RESYNC_CNTL  832 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
PIXCLK_RESYNC_CNTL  836 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_UPDATE(PIXCLK_RESYNC_CNTL,
PIXCLK_RESYNC_CNTL   42 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
PIXCLK_RESYNC_CNTL   60 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
PIXCLK_RESYNC_CNTL   83 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
PIXCLK_RESYNC_CNTL  109 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
PIXCLK_RESYNC_CNTL  152 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	uint32_t PIXCLK_RESYNC_CNTL;