odn_table         822 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table         837 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	odn_table->odn_core_clock_dpm_levels.num_of_pl =
odn_table         839 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	entries = odn_table->odn_core_clock_dpm_levels.entries;
odn_table         847 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
odn_table         849 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	odn_table->odn_memory_clock_dpm_levels.num_of_pl =
odn_table         851 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	entries = odn_table->odn_memory_clock_dpm_levels.entries;
odn_table         859 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
odn_table         895 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table         907 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
odn_table         915 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
odn_table         923 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
odn_table         933 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
odn_table        3761 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table        3762 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
odn_table        3763 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
odn_table        4448 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table        4449 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
odn_table        4450 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
odn_table         306 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table         321 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	od_lookup_table = &odn_table->vddc_lookup_table;
odn_table         332 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
odn_table         333 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
odn_table         334 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
odn_table         339 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
odn_table         340 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
odn_table         341 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
odn_table         342 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		odn_table->min_vddc = dep_table[0]->entries[0].vddc;
odn_table         348 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
odn_table         349 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					odn_table->max_vddc :
odn_table        2459 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table        2466 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
odn_table        2476 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
odn_table        2501 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table        2510 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (odn_table->max_vddc) {
odn_table        3334 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
odn_table        3335 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
odn_table        3346 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	odn_clk_table = &odn_table->vdd_dep_on_mclk;
odn_table        4994 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
odn_table        4997 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
odn_table        4998 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);