odf 1307 drivers/clk/clk-stm32h7.c int odf; odf 1316 drivers/clk/clk-stm32h7.c for (odf = 0; odf < 3; odf++) { odf 1317 drivers/clk/clk-stm32h7.c int idx = n * 3 + odf; odf 1319 drivers/clk/clk-stm32h7.c get_cfg_composite_div(&odf_clk_gcfg, &stm32_odf[n][odf], odf 1323 drivers/clk/clk-stm32h7.c stm32_odf[n][odf].name, odf 1324 drivers/clk/clk-stm32h7.c stm32_odf[n][odf].parent_name, odf 1325 drivers/clk/clk-stm32h7.c stm32_odf[n][odf].num_parents, odf 1329 drivers/clk/clk-stm32h7.c stm32_odf[n][odf].flags); odf 52 drivers/clk/st/clkgen-pll.c struct clkgen_field odf[C32_MAX_ODFS]; odf 72 drivers/clk/st/clkgen-pll.c .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) }, odf 85 drivers/clk/st/clkgen-pll.c .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) }, odf 98 drivers/clk/st/clkgen-pll.c .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) }, odf 115 drivers/clk/st/clkgen-pll.c .odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) }, odf 150 drivers/clk/st/clkgen-pll.c u32 odf; odf 160 drivers/clk/st/clkgen-pll.c unsigned long odf; odf 640 drivers/clk/st/clkgen-pll.c unsigned long pll_flags, int odf, odf 656 drivers/clk/st/clkgen-pll.c gate->reg = reg + pll_data->odf_gate[odf].offset; odf 657 drivers/clk/st/clkgen-pll.c gate->bit_idx = pll_data->odf_gate[odf].shift; odf 667 drivers/clk/st/clkgen-pll.c div->reg = reg + pll_data->odf[odf].offset; odf 668 drivers/clk/st/clkgen-pll.c div->shift = pll_data->odf[odf].shift; odf 669 drivers/clk/st/clkgen-pll.c div->width = fls(pll_data->odf[odf].mask); odf 694 drivers/clk/st/clkgen-pll.c int num_odfs, odf; odf 729 drivers/clk/st/clkgen-pll.c for (odf = 0; odf < num_odfs; odf++) { odf 735 drivers/clk/st/clkgen-pll.c odf, &clk_name)) odf 738 drivers/clk/st/clkgen-pll.c of_clk_detect_critical(np, odf, &odf_flags); odf 741 drivers/clk/st/clkgen-pll.c odf, &clkgena_c32_odf_lock, clk_name); odf 745 drivers/clk/st/clkgen-pll.c clk_data->clks[odf] = clk; odf 48 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c uint32_t odf; odf 79 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c u32 val, tmdsck, idf, odf, pllctrl = 0; odf 89 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c odf = plldividers[i].odf; odf 111 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c pllctrl |= odf << PLL_CFG_ODF_SHIFT; odf 130 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) odf 132 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c int divisor = idf * odf; odf 143 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c int *idf, int *ndiv, int *odf) odf 185 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c *odf = o; odf 246 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; odf 277 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c odf = 0; odf 279 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c &idf, &ndiv, &odf); odf 284 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); odf 288 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); odf 804 drivers/media/dvb-frontends/stv0910.c u32 odf = 4; odf 807 drivers/media/dvb-frontends/stv0910.c u32 ndiv = (fphi * odf * idf) / quartz; odf 855 drivers/media/dvb-frontends/stv0910.c write_reg(state, RSTV0910_NCOARSE2, odf); odf 859 drivers/media/dvb-frontends/stv0910.c state->base->mclk = fvco / (2 * odf) * 1000000;