od3               454 drivers/gpu/drm/meson/meson_vclk.c 			       unsigned int od2, unsigned int od3)
od3               572 drivers/gpu/drm/meson/meson_vclk.c 				3 << 18, pll_od_to_reg(od3) << 18);
od3               576 drivers/gpu/drm/meson/meson_vclk.c 				3 << 19, pll_od_to_reg(od3) << 19);
od3               579 drivers/gpu/drm/meson/meson_vclk.c 				3 << 20, pll_od_to_reg(od3) << 20);
od3               701 drivers/gpu/drm/meson/meson_vclk.c 	unsigned int od, m, frac, od1, od2, od3;
od3               704 drivers/gpu/drm/meson/meson_vclk.c 		od3 = 1;
od3               714 drivers/gpu/drm/meson/meson_vclk.c 				 pll_freq, m, frac, od1, od2, od3);
od3               716 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
od3               749 drivers/gpu/drm/meson/meson_vclk.c 			   unsigned int od1, unsigned int od2, unsigned int od3,
od3               765 drivers/gpu/drm/meson/meson_vclk.c 	if (!od1 && !od2 && !od3) {
od3               783 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
od3               801 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
od3               818 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);