od2               454 drivers/gpu/drm/meson/meson_vclk.c 			       unsigned int od2, unsigned int od3)
od2               561 drivers/gpu/drm/meson/meson_vclk.c 				3 << 22, pll_od_to_reg(od2) << 22);
od2               565 drivers/gpu/drm/meson/meson_vclk.c 				3 << 23, pll_od_to_reg(od2) << 23);
od2               568 drivers/gpu/drm/meson/meson_vclk.c 				3 << 18, pll_od_to_reg(od2) << 18);
od2               701 drivers/gpu/drm/meson/meson_vclk.c 	unsigned int od, m, frac, od1, od2, od3;
od2               707 drivers/gpu/drm/meson/meson_vclk.c 			od2 = 1;
od2               709 drivers/gpu/drm/meson/meson_vclk.c 			od2 = od / 4;
od2               710 drivers/gpu/drm/meson/meson_vclk.c 			od1 = od / od2;
od2               714 drivers/gpu/drm/meson/meson_vclk.c 				 pll_freq, m, frac, od1, od2, od3);
od2               716 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
od2               749 drivers/gpu/drm/meson/meson_vclk.c 			   unsigned int od1, unsigned int od2, unsigned int od3,
od2               765 drivers/gpu/drm/meson/meson_vclk.c 	if (!od1 && !od2 && !od3) {
od2               783 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
od2               801 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
od2               818 drivers/gpu/drm/meson/meson_vclk.c 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);