octeon_irq_chip_ciu2_mbox 1855 arch/mips/cavium-octeon/octeon-irq.c static struct irq_chip octeon_irq_chip_ciu2_mbox = {
octeon_irq_chip_ciu2_mbox 2092 arch/mips/cavium-octeon/octeon-irq.c 	irq_set_chip_and_handler(OCTEON_IRQ_MBOX0, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
octeon_irq_chip_ciu2_mbox 2093 arch/mips/cavium-octeon/octeon-irq.c 	irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
octeon_irq_chip_ciu2_mbox 2094 arch/mips/cavium-octeon/octeon-irq.c 	irq_set_chip_and_handler(OCTEON_IRQ_MBOX2, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);
octeon_irq_chip_ciu2_mbox 2095 arch/mips/cavium-octeon/octeon-irq.c 	irq_set_chip_and_handler(OCTEON_IRQ_MBOX3, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);