ocsc_mode 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c uint32_t ocsc_mode; ocsc_mode 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c ocsc_mode = 4; ocsc_mode 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c ocsc_mode = 5; ocsc_mode 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c if (ocsc_mode == 4) { ocsc_mode 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); ocsc_mode 630 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; ocsc_mode 641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ocsc_mode); ocsc_mode 647 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ocsc_mode); ocsc_mode 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c enum mpc_output_csc_mode ocsc_mode) ocsc_mode 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); ocsc_mode 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) ocsc_mode 153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { ocsc_mode 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c enum mpc_output_csc_mode ocsc_mode) ocsc_mode 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); ocsc_mode 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) ocsc_mode 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { ocsc_mode 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h enum mpc_output_csc_mode ocsc_mode); ocsc_mode 279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h enum mpc_output_csc_mode ocsc_mode); ocsc_mode 246 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h enum mpc_output_csc_mode ocsc_mode); ocsc_mode 251 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h enum mpc_output_csc_mode ocsc_mode);