oclass 30 drivers/gpu/drm/nouveau/dispnv50/base.c s32 oclass; oclass 52 drivers/gpu/drm/nouveau/dispnv50/base.c return bases[cid].new(drm, head, bases[cid].oclass, pwndw); oclass 7 drivers/gpu/drm/nouveau/dispnv50/base.h struct nouveau_drm *, int head, s32 oclass, oclass 259 drivers/gpu/drm/nouveau/dispnv50/base507c.c struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data, oclass 276 drivers/gpu/drm/nouveau/dispnv50/base507c.c &oclass, head, &args, sizeof(args), oclass 279 drivers/gpu/drm/nouveau/dispnv50/base507c.c NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret); oclass 299 drivers/gpu/drm/nouveau/dispnv50/base507c.c base507c_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 302 drivers/gpu/drm/nouveau/dispnv50/base507c.c return base507c_new_(&base507c, base507c_format, drm, head, oclass, oclass 75 drivers/gpu/drm/nouveau/dispnv50/base827c.c base827c_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 78 drivers/gpu/drm/nouveau/dispnv50/base827c.c return base507c_new_(&base827c, base507c_format, drm, head, oclass, oclass 171 drivers/gpu/drm/nouveau/dispnv50/base907c.c base907c_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 174 drivers/gpu/drm/nouveau/dispnv50/base907c.c return base507c_new_(&base907c, base507c_format, drm, head, oclass, oclass 45 drivers/gpu/drm/nouveau/dispnv50/base917c.c base917c_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 48 drivers/gpu/drm/nouveau/dispnv50/base917c.c return base507c_new_(&base907c, base917c_format, drm, head, oclass, oclass 41 drivers/gpu/drm/nouveau/dispnv50/core.c s32 oclass; oclass 70 drivers/gpu/drm/nouveau/dispnv50/core.c return cores[cid].new(drm, cores[cid].oclass, pcore); oclass 89 drivers/gpu/drm/nouveau/dispnv50/core507d.c s32 oclass, struct nv50_core **pcore) oclass 101 drivers/gpu/drm/nouveau/dispnv50/core507d.c &oclass, 0, &args, sizeof(args), oclass 104 drivers/gpu/drm/nouveau/dispnv50/core507d.c NV_ERROR(drm, "core%04x allocation failed: %d\n", oclass, ret); oclass 112 drivers/gpu/drm/nouveau/dispnv50/core507d.c core507d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) oclass 114 drivers/gpu/drm/nouveau/dispnv50/core507d.c return core507d_new_(&core507d, drm, oclass, pcore); oclass 38 drivers/gpu/drm/nouveau/dispnv50/core827d.c core827d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) oclass 40 drivers/gpu/drm/nouveau/dispnv50/core827d.c return core507d_new_(&core827d, drm, oclass, pcore); oclass 37 drivers/gpu/drm/nouveau/dispnv50/core907d.c core907d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) oclass 39 drivers/gpu/drm/nouveau/dispnv50/core907d.c return core507d_new_(&core907d, drm, oclass, pcore); oclass 37 drivers/gpu/drm/nouveau/dispnv50/core917d.c core917d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) oclass 39 drivers/gpu/drm/nouveau/dispnv50/core917d.c return core507d_new_(&core917d, drm, oclass, pcore); oclass 107 drivers/gpu/drm/nouveau/dispnv50/corec37d.c corec37d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) oclass 109 drivers/gpu/drm/nouveau/dispnv50/corec37d.c return core507d_new_(&corec37d, drm, oclass, pcore); oclass 58 drivers/gpu/drm/nouveau/dispnv50/corec57d.c corec57d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore) oclass 60 drivers/gpu/drm/nouveau/dispnv50/corec57d.c return core507d_new_(&corec57d, drm, oclass, pcore); oclass 30 drivers/gpu/drm/nouveau/dispnv50/curs.c s32 oclass; oclass 52 drivers/gpu/drm/nouveau/dispnv50/curs.c return curses[cid].new(drm, head, curses[cid].oclass, pwndw); oclass 7 drivers/gpu/drm/nouveau/dispnv50/curs.h int head, s32 oclass, u32 interlock_data, oclass 110 drivers/gpu/drm/nouveau/dispnv50/curs507a.c int head, s32 oclass, u32 interlock_data, oclass 126 drivers/gpu/drm/nouveau/dispnv50/curs507a.c ret = nvif_object_init(&disp->disp->object, 0, oclass, &args, oclass 129 drivers/gpu/drm/nouveau/dispnv50/curs507a.c NV_ERROR(drm, "curs%04x allocation failed: %d\n", oclass, ret); oclass 140 drivers/gpu/drm/nouveau/dispnv50/curs507a.c curs507a_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 143 drivers/gpu/drm/nouveau/dispnv50/curs507a.c return curs507a_new_(&curs507a, drm, head, oclass, oclass 25 drivers/gpu/drm/nouveau/dispnv50/curs907a.c curs907a_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 28 drivers/gpu/drm/nouveau/dispnv50/curs907a.c return curs507a_new_(&curs507a, drm, head, oclass, oclass 45 drivers/gpu/drm/nouveau/dispnv50/cursc37a.c cursc37a_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 48 drivers/gpu/drm/nouveau/dispnv50/cursc37a.c return curs507a_new_(&cursc37a, drm, head, oclass, oclass 82 drivers/gpu/drm/nouveau/dispnv50/disp.c const s32 *oclass, u8 head, void *data, u32 size, oclass 94 drivers/gpu/drm/nouveau/dispnv50/disp.c while (oclass[0]) { oclass 96 drivers/gpu/drm/nouveau/dispnv50/disp.c if (sclass[i].oclass == oclass[0]) { oclass 97 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nvif_object_init(disp, 0, oclass[0], oclass 105 drivers/gpu/drm/nouveau/dispnv50/disp.c oclass++; oclass 135 drivers/gpu/drm/nouveau/dispnv50/disp.c const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, oclass 165 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_chan_create(device, disp, oclass, head, data, size, oclass 1614 drivers/gpu/drm/nouveau/dispnv50/disp.c if (disp->disp->object.oclass < GF110_DISP) { oclass 2365 drivers/gpu/drm/nouveau/dispnv50/disp.c if (disp->disp->object.oclass >= GV100_DISP) oclass 2368 drivers/gpu/drm/nouveau/dispnv50/disp.c if (disp->disp->object.oclass >= GF110_DISP) oclass 72 drivers/gpu/drm/nouveau/dispnv50/disp.h const s32 *oclass, u8 head, void *data, u32 size, oclass 493 drivers/gpu/drm/nouveau/dispnv50/head.c if (disp->disp->object.oclass < GV100_DISP) { oclass 514 drivers/gpu/drm/nouveau/dispnv50/head.c if (disp->disp->object.oclass >= GF110_DISP) oclass 70 drivers/gpu/drm/nouveau/dispnv50/lut.c const u32 size = disp->disp->object.oclass < GF110_DISP ? 257 : 1025; oclass 30 drivers/gpu/drm/nouveau/dispnv50/oimm.c s32 oclass; oclass 50 drivers/gpu/drm/nouveau/dispnv50/oimm.c return oimms[cid].init(drm, oimms[cid].oclass, wndw); oclass 28 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c s32 oclass, struct nv50_wndw *wndw) oclass 36 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c ret = nvif_object_init(&disp->disp->object, 0, oclass, &args, oclass 39 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c NV_ERROR(drm, "oimm%04x allocation failed: %d\n", oclass, ret); oclass 49 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c oimm507b_init(struct nouveau_drm *drm, s32 oclass, struct nv50_wndw *wndw) oclass 51 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c return oimm507b_init_(&curs507a, drm, oclass, wndw); oclass 31 drivers/gpu/drm/nouveau/dispnv50/ovly.c s32 oclass; oclass 52 drivers/gpu/drm/nouveau/dispnv50/ovly.c ret = ovlys[cid].new(drm, head, ovlys[cid].oclass, pwndw); oclass 7 drivers/gpu/drm/nouveau/dispnv50/ovly.h struct nouveau_drm *, int head, s32 oclass, oclass 170 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data, oclass 188 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c &oclass, 0, &args, sizeof(args), oclass 191 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c NV_ERROR(drm, "ovly%04x allocation failed: %d\n", oclass, ret); oclass 211 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ovly507e_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 214 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c return ovly507e_new_(&ovly507e, ovly507e_format, drm, head, oclass, oclass 99 drivers/gpu/drm/nouveau/dispnv50/ovly827e.c ovly827e_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 102 drivers/gpu/drm/nouveau/dispnv50/ovly827e.c return ovly507e_new_(&ovly827e, ovly827e_format, drm, head, oclass, oclass 76 drivers/gpu/drm/nouveau/dispnv50/ovly907e.c ovly907e_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 79 drivers/gpu/drm/nouveau/dispnv50/ovly907e.c return ovly507e_new_(&ovly907e, ovly907e_format, drm, head, oclass, oclass 37 drivers/gpu/drm/nouveau/dispnv50/ovly917e.c ovly917e_new(struct nouveau_drm *drm, int head, s32 oclass, oclass 40 drivers/gpu/drm/nouveau/dispnv50/ovly917e.c return ovly507e_new_(&ovly907e, ovly917e_format, drm, head, oclass, oclass 30 drivers/gpu/drm/nouveau/dispnv50/wimm.c s32 oclass; oclass 47 drivers/gpu/drm/nouveau/dispnv50/wimm.c return wimms[cid].init(drm, wimms[cid].oclass, wndw); oclass 61 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c s32 oclass, struct nv50_wndw *wndw) oclass 71 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c &oclass, 0, &args, sizeof(args), 0, oclass 74 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c NV_ERROR(drm, "wimm%04x allocation failed: %d\n", oclass, ret); oclass 84 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c wimmc37b_init(struct nouveau_drm *drm, s32 oclass, struct nv50_wndw *wndw) oclass 86 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c return wimmc37b_init_(&wimmc37b, drm, oclass, wndw); oclass 703 drivers/gpu/drm/nouveau/dispnv50/wndw.c s32 oclass; oclass 721 drivers/gpu/drm/nouveau/dispnv50/wndw.c ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw); oclass 103 drivers/gpu/drm/nouveau/dispnv50/wndw.h enum drm_plane_type type, int index, s32 oclass, u32 heads, oclass 277 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c enum drm_plane_type type, int index, s32 oclass, u32 heads, oclass 295 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c &oclass, 0, &args, sizeof(args), oclass 298 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c NV_ERROR(drm, "qndw%04x allocation failed: %d\n", oclass, ret); oclass 310 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c s32 oclass, struct nv50_wndw **pwndw) oclass 312 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c return wndwc37e_new_(&wndwc37e, drm, type, index, oclass, oclass 199 drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c s32 oclass, struct nv50_wndw **pwndw) oclass 201 drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c return wndwc37e_new_(&wndwc57e, drm, type, index, oclass, oclass 21 drivers/gpu/drm/nouveau/include/nvif/device.h int nvif_device_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32, oclass 10 drivers/gpu/drm/nouveau/include/nvif/disp.h int nvif_disp_ctor(struct nvif_device *, s32 oclass, struct nvif_disp *); oclass 45 drivers/gpu/drm/nouveau/include/nvif/ioctl.h __s32 oclass; oclass 48 drivers/gpu/drm/nouveau/include/nvif/ioctl.h } oclass[]; oclass 59 drivers/gpu/drm/nouveau/include/nvif/ioctl.h __s32 oclass; oclass 13 drivers/gpu/drm/nouveau/include/nvif/mem.h int nvif_mem_init_type(struct nvif_mmu *mmu, s32 oclass, int type, u8 page, oclass 15 drivers/gpu/drm/nouveau/include/nvif/mem.h int nvif_mem_init(struct nvif_mmu *mmu, s32 oclass, u8 type, u8 page, oclass 33 drivers/gpu/drm/nouveau/include/nvif/mmu.h int nvif_mmu_init(struct nvif_object *, s32 oclass, struct nvif_mmu *); oclass 8 drivers/gpu/drm/nouveau/include/nvif/object.h s32 oclass; oclass 16 drivers/gpu/drm/nouveau/include/nvif/object.h s32 oclass; oclass 24 drivers/gpu/drm/nouveau/include/nvif/object.h int nvif_object_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32, oclass 74 drivers/gpu/drm/nouveau/include/nvif/object.h s32 oclass; oclass 87 drivers/gpu/drm/nouveau/include/nvif/object.h for (i = 0; ret < 0 && mclass[i].oclass; i++) { \ oclass 89 drivers/gpu/drm/nouveau/include/nvif/object.h if (mclass[i].oclass == sclass[j].oclass && \ oclass 107 drivers/gpu/drm/nouveau/include/nvif/object.h for (_cid = 0; _mclass[_cid].oclass; _cid++) { \ oclass 108 drivers/gpu/drm/nouveau/include/nvif/object.h if (_mclass[_cid].oclass == _oclass) \ oclass 111 drivers/gpu/drm/nouveau/include/nvif/object.h _cid = _mclass[_cid].oclass ? _cid : -ENOSYS; \ oclass 33 drivers/gpu/drm/nouveau/include/nvif/vmm.h int nvif_vmm_init(struct nvif_mmu *, s32 oclass, bool managed, u64 addr, oclass 42 drivers/gpu/drm/nouveau/include/nvkm/core/client.h _object->handle, _object->oclass, ##a); \ oclass 12 drivers/gpu/drm/nouveau/include/nvkm/core/object.h s32 oclass; oclass 11 drivers/gpu/drm/nouveau/include/nvkm/core/oclass.h s32 oclass; oclass 431 drivers/gpu/drm/nouveau/nouveau_abi16.c s32 oclass = 0; oclass 451 drivers/gpu/drm/nouveau/nouveau_abi16.c for (i = 0; !oclass && i < ret; i++) { oclass 452 drivers/gpu/drm/nouveau/nouveau_abi16.c switch (sclass[i].oclass) { oclass 457 drivers/gpu/drm/nouveau/nouveau_abi16.c oclass = sclass[i].oclass; oclass 467 drivers/gpu/drm/nouveau/nouveau_abi16.c if ((sclass[i].oclass & 0x00ff) == 0x00b1) { oclass 468 drivers/gpu/drm/nouveau/nouveau_abi16.c oclass = sclass[i].oclass; oclass 476 drivers/gpu/drm/nouveau/nouveau_abi16.c if ((sclass[i].oclass & 0x00ff) == 0x00b2) { oclass 477 drivers/gpu/drm/nouveau/nouveau_abi16.c oclass = sclass[i].oclass; oclass 485 drivers/gpu/drm/nouveau/nouveau_abi16.c if ((sclass[i].oclass & 0x00ff) == 0x00b3) { oclass 486 drivers/gpu/drm/nouveau/nouveau_abi16.c oclass = sclass[i].oclass; oclass 491 drivers/gpu/drm/nouveau/nouveau_abi16.c oclass = init->class; oclass 495 drivers/gpu/drm/nouveau/nouveau_abi16.c if (!oclass) oclass 505 drivers/gpu/drm/nouveau/nouveau_abi16.c ret = nvif_object_init(&chan->chan->user, init->handle, oclass, oclass 284 drivers/gpu/drm/nouveau/nouveau_bo.c if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) oclass 1168 drivers/gpu/drm/nouveau/nouveau_bo.c s32 oclass; oclass 1210 drivers/gpu/drm/nouveau/nouveau_bo.c mthd->oclass | (mthd->engine << 16), oclass 1211 drivers/gpu/drm/nouveau/nouveau_bo.c mthd->oclass, NULL, 0, oclass 1464 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) oclass 1472 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { oclass 1481 drivers/gpu/drm/nouveau/nouveau_bo.c switch (mem->mem.object.oclass) { oclass 1522 drivers/gpu/drm/nouveau/nouveau_bo.c if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { oclass 239 drivers/gpu/drm/nouveau/nouveau_chan.c const u16 *oclass = oclasses; oclass 258 drivers/gpu/drm/nouveau/nouveau_chan.c if (oclass[0] >= VOLTA_CHANNEL_GPFIFO_A) { oclass 267 drivers/gpu/drm/nouveau/nouveau_chan.c if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { oclass 276 drivers/gpu/drm/nouveau/nouveau_chan.c if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { oclass 291 drivers/gpu/drm/nouveau/nouveau_chan.c ret = nvif_object_init(&device->object, 0, *oclass++, oclass 294 drivers/gpu/drm/nouveau/nouveau_chan.c if (chan->user.oclass >= VOLTA_CHANNEL_GPFIFO_A) { oclass 299 drivers/gpu/drm/nouveau/nouveau_chan.c if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) { oclass 303 drivers/gpu/drm/nouveau/nouveau_chan.c if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { oclass 310 drivers/gpu/drm/nouveau/nouveau_chan.c } while (*oclass); oclass 325 drivers/gpu/drm/nouveau/nouveau_chan.c const u16 *oclass = oclasses; oclass 342 drivers/gpu/drm/nouveau/nouveau_chan.c ret = nvif_object_init(&device->object, 0, *oclass++, oclass 348 drivers/gpu/drm/nouveau/nouveau_chan.c } while (ret && *oclass); oclass 364 drivers/gpu/drm/nouveau/nouveau_chan.c if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { oclass 422 drivers/gpu/drm/nouveau/nouveau_chan.c switch (chan->user.oclass & 0x00ff) { oclass 154 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->disp.object.oclass < NV50_DISP) oclass 271 drivers/gpu/drm/nouveau/nouveau_connector.c if (nouveau_display(connector->dev)->disp.object.oclass < NV50_DISP) { oclass 331 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->disp.object.oclass < NV50_DISP) oclass 1385 drivers/gpu/drm/nouveau/nouveau_connector.c if ((disp->disp.object.oclass >= G82_DISP) oclass 1407 drivers/gpu/drm/nouveau/nouveau_connector.c if (disp->disp.object.oclass < NV50_DISP) { oclass 466 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->disp.object.oclass < NV50_DISP) oclass 469 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->disp.object.oclass < GF110_DISP) oclass 548 drivers/gpu/drm/nouveau/nouveau_display.c if (disp->disp.object.oclass < NV50_DISP) oclass 475 drivers/gpu/drm/nouveau/nouveau_dmem.c switch (drm->ttm.copy.oclass) { oclass 257 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu); oclass 269 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); oclass 445 drivers/gpu/drm/nouveau/nouveau_drm.c switch (sclass[i].oclass) { oclass 71 drivers/gpu/drm/nouveau/nouveau_gem.c if (vmm->vmm.object.oclass < NVIF_CLASS_VMM_NV50) oclass 146 drivers/gpu/drm/nouveau/nouveau_gem.c if (vmm->vmm.object.oclass < NVIF_CLASS_VMM_NV50) oclass 236 drivers/gpu/drm/nouveau/nouveau_gem.c if (vmm->vmm.object.oclass >= NVIF_CLASS_VMM_NV50) { oclass 344 drivers/gpu/drm/nouveau/nouveau_gem.c if (chan->vmm->vmm.object.oclass >= NVIF_CLASS_VMM_NV50) { oclass 439 drivers/gpu/drm/nouveau/nouveau_gem.c if (chan->vmm->vmm.object.oclass >= NVIF_CLASS_VMM_NV50) { oclass 47 drivers/gpu/drm/nouveau/nouveau_mem.c switch (vmm->object.oclass) { oclass 114 drivers/gpu/drm/nouveau/nouveau_mem.c if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) oclass 124 drivers/gpu/drm/nouveau/nouveau_mem.c ret = nvif_mem_init_type(mmu, cli->mem->oclass, type, PAGE_SHIFT, oclass 145 drivers/gpu/drm/nouveau/nouveau_mem.c switch (cli->mem->oclass) { oclass 147 drivers/gpu/drm/nouveau/nouveau_mem.c ret = nvif_mem_init_type(mmu, cli->mem->oclass, oclass 155 drivers/gpu/drm/nouveau/nouveau_mem.c ret = nvif_mem_init_type(mmu, cli->mem->oclass, oclass 338 drivers/gpu/drm/nouveau/nouveau_svm.c ret = nvif_vmm_init(&cli->mmu, cli->vmm.vmm.object.oclass, true, oclass 778 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_fault_buffer_ctor(struct nouveau_svm *svm, s32 oclass, int id) oclass 788 drivers/gpu/drm/nouveau/nouveau_svm.c ret = nvif_object_init(device, 0, oclass, &args, sizeof(args), oclass 872 drivers/gpu/drm/nouveau/nouveau_svm.c ret = nouveau_svm_fault_buffer_ctor(svm, buffers[ret].oclass, 0); oclass 129 drivers/gpu/drm/nouveau/nouveau_vmm.c nouveau_vmm_init(struct nouveau_cli *cli, s32 oclass, struct nouveau_vmm *vmm) oclass 131 drivers/gpu/drm/nouveau/nouveau_vmm.c int ret = nvif_vmm_init(&cli->mmu, oclass, false, PAGE_SIZE, 0, NULL, 0, oclass 31 drivers/gpu/drm/nouveau/nouveau_vmm.h int nouveau_vmm_init(struct nouveau_cli *, s32 oclass, struct nouveau_vmm *); oclass 47 drivers/gpu/drm/nouveau/nvif/device.c nvif_device_init(struct nvif_object *parent, u32 handle, s32 oclass, oclass 50 drivers/gpu/drm/nouveau/nvif/device.c int ret = nvif_object_init(parent, handle, oclass, data, size, oclass 34 drivers/gpu/drm/nouveau/nvif/disp.c nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp) oclass 54 drivers/gpu/drm/nouveau/nvif/disp.c int cid = nvif_sclass(&device->object, disps, oclass); oclass 59 drivers/gpu/drm/nouveau/nvif/disp.c return nvif_object_init(&device->object, 0, disps[cid].oclass, oclass 47 drivers/gpu/drm/nouveau/nvif/mem.c nvif_mem_init_type(struct nvif_mmu *mmu, s32 oclass, int type, u8 page, oclass 70 drivers/gpu/drm/nouveau/nvif/mem.c ret = nvif_object_init(&mmu->object, 0, oclass, args, oclass 86 drivers/gpu/drm/nouveau/nvif/mem.c nvif_mem_init(struct nvif_mmu *mmu, s32 oclass, u8 type, u8 page, oclass 95 drivers/gpu/drm/nouveau/nvif/mem.c ret = nvif_mem_init_type(mmu, oclass, i, page, size, oclass 37 drivers/gpu/drm/nouveau/nvif/mmu.c nvif_mmu_init(struct nvif_object *parent, s32 oclass, struct nvif_mmu *mmu) oclass 53 drivers/gpu/drm/nouveau/nvif/mmu.c ret = nvif_object_init(parent, 0, oclass, &args, sizeof(args), oclass 66 drivers/gpu/drm/nouveau/nvif/mmu.c mmu->mem = mems[ret].oclass; oclass 69 drivers/gpu/drm/nouveau/nvif/object.c size = sizeof(*args) + cnt * sizeof(args->sclass.oclass[0]); oclass 89 drivers/gpu/drm/nouveau/nvif/object.c (*psclass)[i].oclass = args->sclass.oclass[i].oclass; oclass 90 drivers/gpu/drm/nouveau/nvif/object.c (*psclass)[i].minver = args->sclass.oclass[i].minver; oclass 91 drivers/gpu/drm/nouveau/nvif/object.c (*psclass)[i].maxver = args->sclass.oclass[i].maxver; oclass 263 drivers/gpu/drm/nouveau/nvif/object.c nvif_object_init(struct nvif_object *parent, u32 handle, s32 oclass, oclass 274 drivers/gpu/drm/nouveau/nvif/object.c object->oclass = oclass; oclass 291 drivers/gpu/drm/nouveau/nvif/object.c args->new.oclass = oclass; oclass 40 drivers/gpu/drm/nouveau/nvif/user.c s32 oclass; oclass 56 drivers/gpu/drm/nouveau/nvif/user.c ret = nvif_object_init(&device->object, 0, users[cid].oclass, NULL, 0, oclass 115 drivers/gpu/drm/nouveau/nvif/vmm.c nvif_vmm_init(struct nvif_mmu *mmu, s32 oclass, bool managed, u64 addr, oclass 133 drivers/gpu/drm/nouveau/nvif/vmm.c ret = nvif_object_init(&mmu->object, 0, oclass, args, argn, oclass 35 drivers/gpu/drm/nouveau/nvkm/core/client.c nvkm_uclient_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 47 drivers/gpu/drm/nouveau/nvkm/core/client.c NULL, oclass->client->ntfy, &client); oclass 53 drivers/gpu/drm/nouveau/nvkm/core/client.c client->object.client = oclass->client; oclass 54 drivers/gpu/drm/nouveau/nvkm/core/client.c client->object.handle = oclass->handle; oclass 55 drivers/gpu/drm/nouveau/nvkm/core/client.c client->object.route = oclass->route; oclass 56 drivers/gpu/drm/nouveau/nvkm/core/client.c client->object.token = oclass->token; oclass 57 drivers/gpu/drm/nouveau/nvkm/core/client.c client->object.object = oclass->object; oclass 58 drivers/gpu/drm/nouveau/nvkm/core/client.c client->debug = oclass->client->debug; oclass 65 drivers/gpu/drm/nouveau/nvkm/core/client.c .oclass = NVIF_CLASS_CLIENT, oclass 231 drivers/gpu/drm/nouveau/nvkm/core/client.c nvkm_client_child_new(const struct nvkm_oclass *oclass, oclass 234 drivers/gpu/drm/nouveau/nvkm/core/client.c return oclass->base.ctor(oclass, data, size, pobject); oclass 239 drivers/gpu/drm/nouveau/nvkm/core/client.c struct nvkm_oclass *oclass) oclass 250 drivers/gpu/drm/nouveau/nvkm/core/client.c oclass->ctor = nvkm_client_child_new; oclass 251 drivers/gpu/drm/nouveau/nvkm/core/client.c oclass->base = *sclass; oclass 291 drivers/gpu/drm/nouveau/nvkm/core/client.c struct nvkm_oclass oclass = { .base = nvkm_uclient_sclass }; oclass 296 drivers/gpu/drm/nouveau/nvkm/core/client.c oclass.client = client; oclass 298 drivers/gpu/drm/nouveau/nvkm/core/client.c nvkm_object_ctor(&nvkm_client, &oclass, &client->object); oclass 56 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c struct nvkm_oclass oclass = { .client = client }; oclass 63 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c if (size != args->v0.count * sizeof(args->v0.oclass[0])) oclass 67 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c object->func->sclass(object, i, &oclass) >= 0) { oclass 69 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c args->v0.oclass[i].oclass = oclass.base.oclass; oclass 70 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c args->v0.oclass[i].minver = oclass.base.minver; oclass 71 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c args->v0.oclass[i].maxver = oclass.base.maxver; oclass 90 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c struct nvkm_oclass oclass; oclass 97 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c args->v0.version, args->v0.handle, args->v0.oclass, oclass 108 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c memset(&oclass, 0x00, sizeof(oclass)); oclass 109 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c oclass.handle = args->v0.handle; oclass 110 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c oclass.route = args->v0.route; oclass 111 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c oclass.token = args->v0.token; oclass 112 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c oclass.object = args->v0.object; oclass 113 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c oclass.client = client; oclass 114 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c oclass.parent = parent; oclass 115 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c ret = parent->func->sclass(parent, i++, &oclass); oclass 118 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c } while (oclass.base.oclass != args->v0.oclass); oclass 120 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c if (oclass.engine) { oclass 121 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c oclass.engine = nvkm_engine_ref(oclass.engine); oclass 122 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c if (IS_ERR(oclass.engine)) oclass 123 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c return PTR_ERR(oclass.engine); oclass 126 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c ret = oclass.ctor(&oclass, data, size, &object); oclass 127 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c nvkm_engine_unref(&oclass.engine); oclass 295 drivers/gpu/drm/nouveau/nvkm/core/object.c const struct nvkm_oclass *oclass, struct nvkm_object *object) oclass 298 drivers/gpu/drm/nouveau/nvkm/core/object.c object->client = oclass->client; oclass 299 drivers/gpu/drm/nouveau/nvkm/core/object.c object->engine = nvkm_engine_ref(oclass->engine); oclass 300 drivers/gpu/drm/nouveau/nvkm/core/object.c object->oclass = oclass->base.oclass; oclass 301 drivers/gpu/drm/nouveau/nvkm/core/object.c object->handle = oclass->handle; oclass 302 drivers/gpu/drm/nouveau/nvkm/core/object.c object->route = oclass->route; oclass 303 drivers/gpu/drm/nouveau/nvkm/core/object.c object->token = oclass->token; oclass 304 drivers/gpu/drm/nouveau/nvkm/core/object.c object->object = oclass->object; oclass 313 drivers/gpu/drm/nouveau/nvkm/core/object.c const struct nvkm_oclass *oclass, void *data, u32 size, oclass 319 drivers/gpu/drm/nouveau/nvkm/core/object.c nvkm_object_ctor(func, oclass, *pobject); oclass 330 drivers/gpu/drm/nouveau/nvkm/core/object.c nvkm_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, oclass 334 drivers/gpu/drm/nouveau/nvkm/core/object.c oclass->base.func ? oclass->base.func : &nvkm_object_func; oclass 335 drivers/gpu/drm/nouveau/nvkm/core/object.c return nvkm_object_new_(func, oclass, data, size, pobject); oclass 99 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c struct nvkm_oclass *oclass) oclass 102 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c oclass->parent = oproxy->object; oclass 105 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c return oproxy->object->func->sclass(oproxy->object, index, oclass); oclass 195 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c const struct nvkm_oclass *oclass, struct nvkm_oproxy *oproxy) oclass 197 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c nvkm_object_ctor(&nvkm_oproxy_func, oclass, &oproxy->base); oclass 203 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c const struct nvkm_oclass *oclass, struct nvkm_oproxy **poproxy) oclass 207 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c nvkm_oproxy_ctor(func, oclass, *poproxy); oclass 41 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c nvkm_wo32(*pgpuobj, 0x00, object->oclass); oclass 192 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c nvkm_control_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, oclass 202 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c nvkm_object_ctor(&nvkm_control, oclass, &ctrl->object); oclass 208 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c .base.oclass = NVIF_CLASS_CONTROL, oclass 336 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c nvkm_udevice_child_new(const struct nvkm_oclass *oclass, oclass 339 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c struct nvkm_udevice *udev = nvkm_udevice(oclass->parent); oclass 340 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c const struct nvkm_device_oclass *sclass = oclass->priv; oclass 341 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c return sclass->ctor(udev->device, oclass, data, size, pobject); oclass 346 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c struct nvkm_oclass *oclass) oclass 362 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c oclass->engine = engine; oclass 364 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index -= engine->func->base.sclass(oclass, index, &sclass); oclass 377 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c oclass->base = sclass->base; oclass 380 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c oclass->ctor = nvkm_udevice_child_new; oclass 381 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c oclass->priv = sclass; oclass 409 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c nvkm_udevice_new(const struct nvkm_oclass *oclass, void *data, u32 size, oclass 415 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c struct nvkm_client *client = oclass->client; oclass 436 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c nvkm_object_ctor(func, oclass, &udev->object); oclass 452 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c .oclass = NV_DEVICE, oclass 165 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c const struct nvkm_oclass *oclass, void *data, u32 size, oclass 168 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c const struct nvkm_disp_oclass *sclass = oclass->engn; oclass 169 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(oclass->engine); oclass 173 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c ret = nvkm_oproxy_new_(&nvkm_disp_class, oclass, &oproxy); oclass 186 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c return sclass->ctor(disp, oclass, data, size, &oproxy->object); oclass 195 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c nvkm_disp_class_get(struct nvkm_oclass *oclass, int index, oclass 198 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(oclass->engine); oclass 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c oclass->base = root->base; oclass 202 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c oclass->engn = root; oclass 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c g84_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/baseg84.c disp, 1, oclass, argv, argc, pobject); oclass 103 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c gf119_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 107 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegf119.c disp, 1, oclass, argv, argc, pobject); oclass 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegp102.c gp102_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/basegp102.c disp, 1, oclass, argv, argc, pobject); oclass 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c struct nvkm_object *parent = oclass->parent; oclass 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c head, push, oclass, pobject); oclass 114 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c nv50_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 118 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c disp, 1, oclass, argv, argc, pobject); oclass 244 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_chan_child_new(const struct nvkm_oclass *oclass, oclass 247 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nv50_disp_chan *chan = nv50_disp_chan(oclass->parent); oclass 250 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const struct nvkm_device_oclass *sclass = oclass->priv; oclass 256 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nvkm_oproxy_ctor(&nv50_disp_chan_child_func_, oclass, &object->oproxy); oclass 260 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c ret = sclass->ctor(device, oclass, argv, argc, &object->oproxy.object); oclass 265 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c oclass->handle); oclass 278 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const struct nvkm_device_oclass *oclass = NULL; oclass 286 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c sclass->engine->func->base.sclass(sclass, index, &oclass); oclass 287 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c if (oclass) { oclass 289 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c sclass->priv = oclass; oclass 341 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const struct nvkm_oclass *oclass, oclass 350 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nvkm_object_ctor(&nv50_disp_chan, oclass, &chan->object); oclass 81 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c g84_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg84.c disp, 0, oclass, argv, argc, pobject); oclass 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c g94_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c disp, 0, oclass, argv, argc, pobject); oclass 224 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c gf119_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 228 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c disp, 0, oclass, argv, argc, pobject); oclass 121 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c gk104_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregk104.c disp, 0, oclass, argv, argc, pobject); oclass 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c gp102_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c disp, 0, oclass, argv, argc, pobject); oclass 199 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c gv100_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 203 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c disp, 0, oclass, argv, argc, pobject); oclass 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c struct nvkm_object *parent = oclass->parent; oclass 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c push, oclass, pobject); oclass 227 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c nv50_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 231 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c disp, 0, oclass, argv, argc, pobject); oclass 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c gf119_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c oclass, argv, argc, pobject); oclass 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgp102.c gp102_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgp102.c oclass, argv, argc, pobject); oclass 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c gv100_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 80 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c oclass, argv, argc, pobject); oclass 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c struct nvkm_object *parent = oclass->parent; oclass 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c head, oclass, pobject); oclass 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c nv50_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 63 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c oclass, argv, argc, pobject); oclass 37 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c const struct nvkm_oclass *oclass, oclass 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c struct nvkm_client *client = oclass->client; oclass 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c ret = nv50_disp_chan_new_(func, mthd, disp, chid, chid, head, oclass, oclass 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c gf119_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c oclass, argv, argc, pobject); oclass 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgp102.c gp102_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgp102.c oclass, argv, argc, pobject); oclass 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c struct nvkm_object *parent = oclass->parent; oclass 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c head, oclass, pobject); oclass 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c nv50_disp_oimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 63 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c oclass, argv, argc, pobject); oclass 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c g84_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlyg84.c disp, 3, oclass, argv, argc, pobject); oclass 90 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c gf119_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygf119.c disp, 5, oclass, argv, argc, pobject); oclass 92 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c gk104_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygk104.c disp, 5, oclass, argv, argc, pobject); oclass 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygp102.c gp102_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygp102.c disp, 5, oclass, argv, argc, pobject); oclass 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c gt200_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlygt200.c disp, 3, oclass, argv, argc, pobject); oclass 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c struct nvkm_object *parent = oclass->parent; oclass 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c head, push, oclass, pobject); oclass 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c nv50_disp_ovly_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c disp, 3, oclass, argv, argc, pobject); oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c g84_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c return nv50_disp_root_new_(&g84_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c .base.oclass = G82_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c g94_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c return nv50_disp_root_new_(&g94_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c .base.oclass = GT206_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c return nv50_disp_root_new_(&gf119_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c .base.oclass = GF110_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c gk104_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c return nv50_disp_root_new_(&gk104_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c .base.oclass = GK104_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c gk110_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c return nv50_disp_root_new_(&gk110_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c .base.oclass = GK110_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c gm107_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c return nv50_disp_root_new_(&gm107_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c .base.oclass = GM107_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c gm200_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c return nv50_disp_root_new_(&gm200_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c .base.oclass = GM200_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c gp100_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c return nv50_disp_root_new_(&gp100_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c .base.oclass = GP100_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c gp102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c return nv50_disp_root_new_(&gp102_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c .base.oclass = GP102_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c gt200_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c return nv50_disp_root_new_(>200_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c .base.oclass = GT200_DISP, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c gt215_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c return nv50_disp_root_new_(>215_disp_root, disp, oclass, oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c .base.oclass = GT214_DISP, oclass 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c gv100_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c return nv50_disp_root_new_(&gv100_disp_root, disp, oclass, oclass 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c .base.oclass = GV100_DISP, oclass 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c nv04_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 88 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c nvkm_object_ctor(&nv04_disp_root, oclass, &root->object); oclass 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c .base.oclass = NV04_DISP, oclass 278 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c nv50_disp_root_child_new_(const struct nvkm_oclass *oclass, oclass 281 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c struct nv50_disp *disp = nv50_disp_root(oclass->parent)->disp; oclass 282 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c const struct nv50_disp_user *user = oclass->priv; oclass 283 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c return user->ctor(oclass, argv, argc, disp, pobject); oclass 319 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c struct nvkm_disp *base, const struct nvkm_oclass *oclass, oclass 329 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c nvkm_object_ctor(&nv50_disp_root_, oclass, &root->object); oclass 348 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c nv50_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 351 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c return nv50_disp_root_new_(&nv50_disp_root, disp, oclass, oclass 357 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c .base.oclass = NV50_DISP, oclass 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c tu102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, oclass 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c return nv50_disp_root_new_(&tu102_disp_root, disp, oclass, oclass 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c .base.oclass = TU102_DISP, oclass 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c struct nvkm_object *parent = oclass->parent; oclass 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c wndw, push, oclass, pobject); oclass 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c gv100_disp_wimm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 81 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c oclass, argv, argc, pobject); oclass 152 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 158 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c struct nvkm_object *parent = oclass->parent; oclass 175 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c wndw, push, oclass, pobject); oclass 179 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c gv100_disp_wndw_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 183 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c disp, 1, oclass, argv, argc, pobject); oclass 33 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c const struct nvkm_oclass *oclass, void *data, u32 size, oclass 36 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c struct nvkm_dma *dma = nvkm_dma(oclass->engine); oclass 40 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c ret = dma->func->class_new(dma, oclass, data, size, &dmaobj); oclass 52 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c nvkm_dma_oclass_fifo_new(const struct nvkm_oclass *oclass, void *data, u32 size, oclass 55 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c return nvkm_dma_oclass_new(oclass->engine->subdev.device, oclass 56 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c oclass, data, size, pobject); oclass 72 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c const struct nvkm_sclass *oclass = &nvkm_dma_sclass[index]; oclass 73 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c sclass->base = oclass[0]; oclass 74 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c sclass->engn = oclass; oclass 82 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c nvkm_dma_oclass_fifo_get(struct nvkm_oclass *oclass, int index) oclass 86 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c oclass->base = nvkm_dma_sclass[index]; oclass 69 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c const struct nvkm_oclass *oclass, void **pdata, u32 *psize, oclass 76 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c struct nvkm_client *client = oclass->client; oclass 77 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c struct nvkm_object *parent = oclass->parent; oclass 84 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c nvkm_object_ctor(&nvkm_dmaobj_func, oclass, &dmaobj->object); oclass 70 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c gf100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, oclass 76 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c struct nvkm_object *parent = oclass->parent; oclass 85 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c ret = nvkm_dmaobj_ctor(&gf100_dmaobj_func, dma, oclass, oclass 117 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass; oclass 68 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c gf119_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, oclass 74 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c struct nvkm_object *parent = oclass->parent; oclass 83 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c ret = nvkm_dmaobj_ctor(&gf119_dmaobj_func, dma, oclass, oclass 67 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c gv100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, oclass 73 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c struct nvkm_object *parent = oclass->parent; oclass 82 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c ret = nvkm_dmaobj_ctor(&gv100_dmaobj_func, dma, oclass, oclass 81 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, oclass 92 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c ret = nvkm_dmaobj_ctor(&nv04_dmaobj_func, dma, oclass, oclass 104 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c dmaobj->flags0 = oclass->base.oclass; oclass 70 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c nv50_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, oclass 76 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c struct nvkm_object *parent = oclass->parent; oclass 85 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c ret = nvkm_dmaobj_ctor(&nv50_dmaobj_func, dma, oclass, oclass 122 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c oclass->base.oclass; oclass 30 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index) oclass 32 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine); oclass 35 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c while (falcon->func->sclass[c].oclass) { oclass 37 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c oclass->base = falcon->func->sclass[index]; oclass 220 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c const struct nvkm_oclass *oclass, void *data, u32 size, oclass 223 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); oclass 224 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c return fifo->func->class_new(fifo, oclass, data, size, pobject); oclass 234 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c const struct nvkm_oclass *oclass, void *data, u32 size, oclass 237 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c const struct nvkm_fifo_chan_oclass *sclass = oclass->engn; oclass 238 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); oclass 239 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c return sclass->ctor(fifo, oclass, data, size, pobject); oclass 248 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index, oclass 251 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); oclass 256 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c int ret = fifo->func->class_get(fifo, index, oclass); oclass 264 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c oclass->base = sclass->base; oclass 265 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c oclass->engn = sclass; oclass 133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, oclass 136 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_engine *engine = oclass->engine; oclass 137 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_fifo_chan *chan = nvkm_fifo_chan(oclass->parent); oclass 144 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c nvkm_oproxy_ctor(&nvkm_fifo_chan_child_func, oclass, &object->oproxy); oclass 150 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .client = oclass->client, oclass 151 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .engine = oclass->engine, oclass 169 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c ret = chan->func->engine_ctor(chan, oclass->engine, oclass 176 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c ret = oclass->base.ctor(&(const struct nvkm_oclass) { oclass 177 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .base = oclass->base, oclass 178 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .engn = oclass->engn, oclass 179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .handle = oclass->handle, oclass 180 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .object = oclass->object, oclass 181 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .client = oclass->client, oclass 184 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->parent, oclass 202 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_oclass *oclass) oclass 214 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->engine = engine; oclass 215 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base.oclass = 0; oclass 218 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c ret = engine->func->fifo.sclass(oclass, index); oclass 219 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (oclass->base.oclass) { oclass 220 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (!oclass->base.ctor) oclass 221 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base.ctor = nvkm_object_new; oclass 222 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->ctor = nvkm_fifo_chan_child_new; oclass 230 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c while (engine->func->sclass[c].oclass) { oclass 232 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base = engine->func->sclass[index]; oclass 233 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (!oclass->base.ctor) oclass 234 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base.ctor = nvkm_object_new; oclass 235 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->ctor = nvkm_fifo_chan_child_new; oclass 356 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c u32 user, const struct nvkm_oclass *oclass, oclass 359 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_client *client = oclass->client; oclass 365 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c nvkm_object_ctor(&nvkm_fifo_chan_func, oclass, &chan->object); oclass 233 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c const struct nvkm_oclass *oclass, oclass 258 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 0, 0xc00000, 0x2000, oclass, &chan->base); oclass 232 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c const struct nvkm_oclass *oclass, oclass 247 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 0, 0xc00000, 0x2000, oclass, &chan->base); oclass 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 37 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c struct nvkm_object *parent = oclass->parent; oclass 61 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c oclass, chan); oclass 90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c .base.oclass = G82_CHANNEL_DMA, oclass 165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 168 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_object *parent = oclass->parent; oclass 197 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 0, 0x800000, 0x10000, oclass, &chan->base); oclass 222 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c .base.oclass = NV03_CHANNEL_DMA, oclass 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c struct nvkm_object *parent = oclass->parent; oclass 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 0, 0x800000, 0x10000, oclass, &chan->base); oclass 93 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c .base.oclass = NV10_CHANNEL_DMA, oclass 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c struct nvkm_object *parent = oclass->parent; oclass 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 0, 0x800000, 0x10000, oclass, &chan->base); oclass 94 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c .base.oclass = NV17_CHANNEL_DMA, oclass 183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 186 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nvkm_object *parent = oclass->parent; oclass 216 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 0, 0xc00000, 0x1000, oclass, &chan->base); oclass 242 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c .base.oclass = NV40_CHANNEL_DMA, oclass 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 37 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c struct nvkm_object *parent = oclass->parent; oclass 61 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c oclass, chan); oclass 88 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c .base.oclass = NV50_CHANNEL_DMA, oclass 99 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_class_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 103 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (oclass->engn == &fifo->func->chan) { oclass 104 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const struct gk104_fifo_chan_user *user = oclass->engn; oclass 105 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c return user->ctor(fifo, oclass, argv, argc, pobject); oclass 107 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (oclass->engn == &fifo->func->user) { oclass 108 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c const struct gk104_fifo_user_user *user = oclass->engn; oclass 109 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c return user->ctor(oclass, argv, argc, pobject); oclass 117 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_oclass *oclass) oclass 123 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->base = fifo->func->user.user; oclass 124 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->engn = &fifo->func->user; oclass 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->base = fifo->func->chan.user; oclass 130 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->engn = &fifo->func->chan; oclass 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 37 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c struct nvkm_object *parent = oclass->parent; oclass 63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c oclass, chan); oclass 91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c .base.oclass = G82_CHANNEL_GPFIFO, oclass 214 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 221 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct nvkm_object *parent = oclass->parent; oclass 254 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c oclass, &chan->base); oclass 297 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c .base.oclass = FERMI_CHANNEL_GPFIFO, oclass 245 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c const struct nvkm_oclass *oclass, oclass 278 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c oclass, &chan->base); oclass 330 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, oclass 333 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct nvkm_object *parent = oclass->parent; oclass 346 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c if (args->v0.priv && !oclass->client->super) oclass 356 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c oclass, pobject); oclass 126 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c u32 *token, const struct nvkm_oclass *oclass, oclass 157 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c oclass, &chan->base); oclass 224 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c gv100_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, oclass 227 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c struct nvkm_object *parent = oclass->parent; oclass 240 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c if (args->v0.priv && !oclass->client->super) oclass 251 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c oclass, pobject); oclass 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, oclass 37 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c struct nvkm_object *parent = oclass->parent; oclass 63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c oclass, chan); oclass 89 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c .base.oclass = NV50_CHANNEL_GPFIFO, oclass 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c tu102_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass, oclass 55 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c struct nvkm_object *parent = oclass->parent; oclass 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c if (args->v0.priv && !oclass->client->super) oclass 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c oclass, pobject); oclass 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/usergv100.c gv100_fifo_user_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 44 drivers/gpu/drm/nouveau/nvkm/engine/fifo/usergv100.c return nvkm_object_new_(&gv100_fifo_user, oclass, argv, argc, pobject); oclass 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/usertu102.c tu102_fifo_user_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 44 drivers/gpu/drm/nouveau/nvkm/engine/fifo/usertu102.c return nvkm_object_new_(&tu102_fifo_user, oclass, argv, argc, pobject); oclass 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_oclass_get(struct nvkm_oclass *oclass, int index) oclass 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(oclass->engine); oclass 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c int ret = gr->func->object_get(gr, index, &oclass->base); oclass 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (oclass->base.oclass) oclass 101 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c while (gr->func->sclass[c].oclass) { oclass 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c oclass->base = gr->func->sclass[index]; oclass 113 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c const struct nvkm_oclass *oclass, oclass 116 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(oclass->engine); oclass 118 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->chan_new(gr, chan, oclass, pobject); oclass 282 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, oclass 285 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent); oclass 292 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_object_ctor(oclass->base.func ? oclass->base.func : oclass 293 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c &gf100_gr_object_func, oclass, &object->object); oclass 304 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c while (gr->func->sclass[c].oclass) { oclass 379 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c const struct nvkm_oclass *oclass, oclass 392 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); oclass 1050 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nvkm_wo32(*pgpuobj, 0x00, object->oclass); oclass 1185 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 1193 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nvkm_object_ctor(&nv04_gr_chan, oclass, &chan->object); oclass 1003 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 1012 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_object_ctor(&nv10_gr_chan, oclass, &chan->object); oclass 76 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 84 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object); oclass 22 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object); oclass 22 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object); oclass 23 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object); oclass 22 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object); oclass 22 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); oclass 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_wo32(*pgpuobj, 0x00, object->oclass); oclass 149 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 157 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nvkm_object_ctor(&nv40_gr_chan, oclass, &chan->object); oclass 50 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_wo32(*pgpuobj, 0x00, object->oclass); oclass 90 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 97 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nvkm_object_ctor(&nv50_gr_chan, oclass, &chan->object); oclass 46 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_wo32(*pgpuobj, 0x00, object->oclass); oclass 85 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c const struct nvkm_oclass *oclass, oclass 88 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c struct nv31_mpeg *mpeg = nv31_mpeg(oclass->engine); oclass 95 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_object_ctor(&nv31_mpeg_chan, oclass, &chan->object); oclass 104 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c const struct nvkm_oclass *oclass, oclass 107 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c struct nv44_mpeg *mpeg = nv44_mpeg(oclass->engine); oclass 113 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c nvkm_object_ctor(&nv44_mpeg_chan, oclass, &chan->object); oclass 367 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c const struct nvkm_oclass *oclass, void *data, u32 size, oclass 374 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c struct nvkm_object *parent = oclass->parent; oclass 418 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_object_ctor(&nvkm_perfdom, oclass, &dom->object); oclass 605 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfmon_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, oclass 608 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c struct nvkm_perfmon *perfmon = nvkm_perfmon(oclass->parent); oclass 609 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c return nvkm_perfdom_new_(perfmon, oclass, data, size, pobject); oclass 614 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c struct nvkm_oclass *oclass) oclass 617 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base.oclass = NVIF_CLASS_PERFDOM; oclass 618 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base.minver = 0; oclass 619 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base.maxver = 0; oclass 620 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->ctor = nvkm_perfmon_child_new; oclass 646 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfmon_new(struct nvkm_pm *pm, const struct nvkm_oclass *oclass, oclass 653 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_object_ctor(&nvkm_perfmon, oclass, &perfmon->object); oclass 664 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_pm_oclass_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, oclass 667 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c struct nvkm_pm *pm = nvkm_pm(oclass->engine); oclass 670 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ret = nvkm_perfmon_new(pm, oclass, data, size, pobject); oclass 684 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c .base.oclass = NVIF_CLASS_PERFMON, oclass 691 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_pm_oclass_get(struct nvkm_oclass *oclass, int index, oclass 695 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base = nvkm_pm_oclass.base; oclass 50 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c nvkm_sw_oclass_new(const struct nvkm_oclass *oclass, void *data, u32 size, oclass 53 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c struct nvkm_sw_chan *chan = nvkm_sw_chan(oclass->parent); oclass 54 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c const struct nvkm_sw_chan_sclass *sclass = oclass->engn; oclass 55 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c return sclass->ctor(chan, oclass, data, size, pobject); oclass 59 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c nvkm_sw_oclass_get(struct nvkm_oclass *oclass, int index) oclass 61 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c struct nvkm_sw *sw = nvkm_sw(oclass->engine); oclass 66 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c oclass->engn = &sw->func->sclass[index]; oclass 67 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c oclass->base = sw->func->sclass[index].base; oclass 68 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c oclass->base.ctor = nvkm_sw_oclass_new; oclass 78 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c const struct nvkm_oclass *oclass, oclass 81 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c struct nvkm_sw *sw = nvkm_sw(oclass->engine); oclass 82 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c return sw->func->chan_new(sw, fifoch, oclass, pobject); oclass 97 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c struct nvkm_fifo_chan *fifo, const struct nvkm_oclass *oclass, oclass 102 drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.c nvkm_object_ctor(&nvkm_sw_chan, oclass, &chan->object); oclass 106 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c const struct nvkm_oclass *oclass, oclass 117 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c ret = nvkm_sw_chan_ctor(&gf100_sw_chan, sw, fifoch, oclass, oclass 77 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c nv04_nvsw_new(struct nvkm_sw_chan *chan, const struct nvkm_oclass *oclass, oclass 80 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c return nvkm_nvsw_new_(&nv04_nvsw, chan, oclass, data, size, pobject); oclass 110 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 119 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c return nvkm_sw_chan_ctor(&nv04_sw_chan, sw, fifo, oclass, &chan->base); oclass 40 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 48 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c return nvkm_sw_chan_ctor(&nv10_sw_chan, sw, fifo, oclass, chan); oclass 101 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c const struct nvkm_oclass *oclass, struct nvkm_object **pobject) oclass 111 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c ret = nvkm_sw_chan_ctor(&nv50_sw_chan, sw, fifoch, oclass, &chan->base); oclass 61 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c const struct nvkm_oclass *oclass, void *data, u32 size, oclass 70 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c nvkm_object_ctor(&nvkm_nvsw_, oclass, &nvsw->object); oclass 81 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c nvkm_nvsw_new(struct nvkm_sw_chan *chan, const struct nvkm_oclass *oclass, oclass 84 drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.c return nvkm_nvsw_new_(&nvkm_nvsw, chan, oclass, data, size, pobject); oclass 28 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_xtensa_oclass_get(struct nvkm_oclass *oclass, int index) oclass 30 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c struct nvkm_xtensa *xtensa = nvkm_xtensa(oclass->engine); oclass 33 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c while (xtensa->func->sclass[c].oclass) { oclass 35 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c oclass->base = xtensa->func->sclass[index]; oclass 86 drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c nvkm_ufault_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, oclass 103 drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.c nvkm_object_ctor(&nvkm_ufault, oclass, &buffer->object); oclass 143 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c nvkm_umem_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 146 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c struct nvkm_mmu *mmu = nvkm_ummu(oclass->parent)->mmu; oclass 167 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c nvkm_object_ctor(&nvkm_umem, oclass, &umem->object); oclass 170 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c umem->priv = oclass->client->super; oclass 33 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c struct nvkm_oclass *oclass) oclass 37 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c if (mmu->func->mem.user.oclass && oclass->client->super) { oclass 39 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c oclass->base = mmu->func->mem.user; oclass 40 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c oclass->ctor = nvkm_umem_new; oclass 45 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c if (mmu->func->vmm.user.oclass) { oclass 47 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c oclass->base = mmu->func->vmm.user; oclass 48 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c oclass->ctor = nvkm_uvmm_new; oclass 151 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c nvkm_ummu_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, oclass 174 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c nvkm_object_ctor(&nvkm_ummu, oclass, &ummu->object); oclass 372 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c nvkm_uvmm_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, oclass 375 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c struct nvkm_mmu *mmu = nvkm_ummu(oclass->parent)->mmu; oclass 376 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c const bool more = oclass->base.maxver >= 0; oclass 395 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c nvkm_object_ctor(&nvkm_uvmm, oclass, &uvmm->object); oclass 404 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c uvmm->vmm->debug = max(uvmm->vmm->debug, oclass->client->debug);