PHYRegDef 581 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A] = &adapter->HalData->PHYRegDef[RF_PATH_A]; PHYRegDef 582 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B] = &adapter->HalData->PHYRegDef[RF_PATH_B]; PHYRegDef 58 drivers/staging/rtl8188eu/hal/phy.c struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath]; PHYRegDef 102 drivers/staging/rtl8188eu/hal/phy.c struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath]; PHYRegDef 228 drivers/staging/rtl8188eu/hal/rf_cfg.c pphyreg = &hal_data->PHYRegDef[RF90_PATH_A]; PHYRegDef 263 drivers/staging/rtl8188eu/include/rtl8188e_hal.h struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */ PHYRegDef 74 drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c pPhyReg = &priv->PHYRegDef[eRFPath]; PHYRegDef 97 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; PHYRegDef 154 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; PHYRegDef 382 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; PHYRegDef 383 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; PHYRegDef 384 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; PHYRegDef 385 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; PHYRegDef 387 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; PHYRegDef 388 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; PHYRegDef 389 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; PHYRegDef 390 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; PHYRegDef 392 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; PHYRegDef 393 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; PHYRegDef 394 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; PHYRegDef 395 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; PHYRegDef 397 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; PHYRegDef 398 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; PHYRegDef 399 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; PHYRegDef 400 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; PHYRegDef 402 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; PHYRegDef 403 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; PHYRegDef 404 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; PHYRegDef 405 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; PHYRegDef 407 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; PHYRegDef 408 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; PHYRegDef 409 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; PHYRegDef 410 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; PHYRegDef 412 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 413 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 414 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 415 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 417 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; PHYRegDef 418 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; PHYRegDef 419 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; PHYRegDef 420 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; PHYRegDef 422 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; PHYRegDef 423 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; PHYRegDef 424 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; PHYRegDef 425 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; PHYRegDef 427 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; PHYRegDef 428 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; PHYRegDef 429 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; PHYRegDef 430 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; PHYRegDef 432 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; PHYRegDef 433 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; PHYRegDef 434 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; PHYRegDef 435 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; PHYRegDef 437 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; PHYRegDef 438 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; PHYRegDef 439 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; PHYRegDef 440 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; PHYRegDef 442 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; PHYRegDef 443 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; PHYRegDef 444 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; PHYRegDef 445 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; PHYRegDef 447 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; PHYRegDef 448 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; PHYRegDef 449 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; PHYRegDef 450 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; PHYRegDef 452 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; PHYRegDef 453 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; PHYRegDef 454 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; PHYRegDef 455 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; PHYRegDef 457 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; PHYRegDef 458 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; PHYRegDef 459 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; PHYRegDef 460 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; PHYRegDef 462 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; PHYRegDef 463 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; PHYRegDef 464 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; PHYRegDef 465 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; PHYRegDef 341 drivers/staging/rtl8192e/rtl8192e/rtl_core.h struct bb_reg_definition PHYRegDef[4]; PHYRegDef 128 drivers/staging/rtl8192u/r8190_rtl8256.c pPhyReg = &priv->PHYRegDef[eRFPath]; PHYRegDef 933 drivers/staging/rtl8192u/r8192U.h BB_REGISTER_DEFINITION_T PHYRegDef[4]; /* Radio A/B/C/D */ PHYRegDef 132 drivers/staging/rtl8192u/r819xU_phy.c BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; PHYRegDef 218 drivers/staging/rtl8192u/r819xU_phy.c BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; PHYRegDef 556 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; PHYRegDef 558 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; PHYRegDef 560 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; PHYRegDef 562 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; PHYRegDef 566 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; PHYRegDef 568 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; PHYRegDef 570 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; PHYRegDef 572 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; PHYRegDef 576 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; PHYRegDef 578 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; PHYRegDef 580 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; PHYRegDef 582 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; PHYRegDef 586 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; PHYRegDef 588 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; PHYRegDef 590 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; PHYRegDef 592 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; PHYRegDef 595 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; PHYRegDef 596 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; PHYRegDef 597 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; PHYRegDef 598 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; PHYRegDef 602 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; PHYRegDef 603 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; PHYRegDef 604 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; PHYRegDef 605 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; PHYRegDef 608 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 609 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 610 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 611 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; PHYRegDef 615 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; PHYRegDef 616 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; PHYRegDef 617 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; PHYRegDef 618 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; PHYRegDef 622 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; PHYRegDef 623 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; PHYRegDef 624 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; PHYRegDef 625 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; PHYRegDef 629 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; PHYRegDef 630 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; PHYRegDef 631 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; PHYRegDef 632 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; PHYRegDef 635 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; PHYRegDef 636 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; PHYRegDef 637 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; PHYRegDef 638 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; PHYRegDef 641 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; PHYRegDef 642 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; PHYRegDef 643 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; PHYRegDef 644 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; PHYRegDef 647 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; PHYRegDef 648 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; PHYRegDef 649 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; PHYRegDef 650 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; PHYRegDef 653 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; PHYRegDef 654 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; PHYRegDef 655 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; PHYRegDef 656 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; PHYRegDef 659 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; PHYRegDef 660 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; PHYRegDef 661 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; PHYRegDef 662 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; PHYRegDef 665 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; PHYRegDef 666 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; PHYRegDef 667 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; PHYRegDef 668 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; PHYRegDef 671 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; PHYRegDef 672 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; PHYRegDef 673 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; PHYRegDef 674 drivers/staging/rtl8192u/r819xU_phy.c priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; PHYRegDef 132 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; PHYRegDef 238 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; PHYRegDef 402 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ PHYRegDef 403 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ PHYRegDef 406 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ PHYRegDef 407 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */ PHYRegDef 410 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ PHYRegDef 411 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ PHYRegDef 413 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ PHYRegDef 414 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; PHYRegDef 416 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ PHYRegDef 417 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */ PHYRegDef 420 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; PHYRegDef 421 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; PHYRegDef 422 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; PHYRegDef 423 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; PHYRegDef 107 drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c pPhyReg = &pHalData->PHYRegDef[eRFPath]; PHYRegDef 357 drivers/staging/rtl8723bs/include/hal_data.h struct bb_register_def PHYRegDef[4]; /* Radio A/B/C/D */