PHYCLKPerState 4051 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, PHYCLKPerState 4064 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { PHYCLKPerState 4093 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { PHYCLKPerState 4123 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.PHYCLKPerState[i] PHYCLKPerState 4083 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, PHYCLKPerState 4096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { PHYCLKPerState 4125 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { PHYCLKPerState 4155 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.PHYCLKPerState[i] PHYCLKPerState 4123 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, PHYCLKPerState 4137 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { PHYCLKPerState 4168 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { PHYCLKPerState 4200 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.PHYCLKPerState[i] PHYCLKPerState 257 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; PHYCLKPerState 399 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h double PHYCLKPerState[DC__VOLTAGE_STATES + 1];