nv_funcs          928 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.pp_smu.dm = ctx;
nv_funcs          929 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_display_count = pp_nv_set_display_count;
nv_funcs          930 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_hard_min_dcfclk_by_freq =
nv_funcs          932 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_min_deep_sleep_dcfclk =
nv_funcs          934 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_voltage_by_freq =
nv_funcs          936 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;
nv_funcs          939 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_pme_wa_enable = NULL;
nv_funcs          941 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
nv_funcs          943 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
nv_funcs          945 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
nv_funcs          946 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
nv_funcs          151 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
nv_funcs          172 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
nv_funcs          212 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
nv_funcs          391 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		pp_smu = &clk_mgr->pp_smu->nv_funcs;
nv_funcs         3401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
nv_funcs         3402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
nv_funcs         3403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
nv_funcs         3408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
nv_funcs         3409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
nv_funcs         3410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
nv_funcs         3608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
nv_funcs         3609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
nv_funcs          298 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 		struct pp_smu_funcs_nv nv_funcs;