nv_crtc 60 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 62 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 64 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; nv_crtc 65 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { nv_crtc 67 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; nv_crtc 75 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 77 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 79 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->sharpness = level; nv_crtc 83 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); nv_crtc 118 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 120 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; nv_crtc 124 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, nv_crtc 157 drivers/gpu/drm/nouveau/dispnv04/crtc.c state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; nv_crtc 166 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); nv_crtc 172 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 179 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->index); nv_crtc 181 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ nv_crtc 184 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->last_dpms = mode; nv_crtc 187 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVSetOwner(dev, nv_crtc->index); nv_crtc 190 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, nv_crtc 219 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVVgaSeqReset(dev, nv_crtc->index, true); nv_crtc 221 drivers/gpu/drm/nouveau/dispnv04/crtc.c seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); nv_crtc 222 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); nv_crtc 223 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); nv_crtc 225 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); nv_crtc 226 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVVgaSeqReset(dev, nv_crtc->index, false); nv_crtc 228 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); nv_crtc 235 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 236 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 460 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 461 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 462 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; nv_crtc 493 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (nv_crtc->index == 0) nv_crtc 499 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (pPriv->overlayCRTC == nv_crtc->index) nv_crtc 529 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); nv_crtc 536 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (nv_crtc->index == 0) nv_crtc 542 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (!nv_crtc->index) nv_crtc 595 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); nv_crtc 609 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 614 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (disp->image[nv_crtc->index]) nv_crtc 615 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(disp->image[nv_crtc->index]); nv_crtc 616 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); nv_crtc 636 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 640 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); nv_crtc 648 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); nv_crtc 661 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 664 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; nv_crtc 666 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; nv_crtc 669 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVSetOwner(crtc->dev, nv_crtc->index); nv_crtc 671 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); nv_crtc 682 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 684 drivers/gpu/drm/nouveau/dispnv04/crtc.c int head = nv_crtc->index; nv_crtc 693 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->last_dpms = NV_DPMS_CLEARED; nv_crtc 700 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 704 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVSetOwner(dev, nv_crtc->index); nv_crtc 709 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVBlankScreen(dev, nv_crtc->index, true); nv_crtc 712 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); nv_crtc 714 drivers/gpu/drm/nouveau/dispnv04/crtc.c uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); nv_crtc 715 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); nv_crtc 723 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 725 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); nv_crtc 731 drivers/gpu/drm/nouveau/dispnv04/crtc.c uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); nv_crtc 733 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); nv_crtc 744 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 746 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (!nv_crtc) nv_crtc 751 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (disp->image[nv_crtc->index]) nv_crtc 752 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(disp->image[nv_crtc->index]); nv_crtc 753 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); nv_crtc 755 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unmap(nv_crtc->cursor.nvbo); nv_crtc 756 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(nv_crtc->cursor.nvbo); nv_crtc 757 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); nv_crtc 758 drivers/gpu/drm/nouveau/dispnv04/crtc.c kfree(nv_crtc); nv_crtc 764 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 765 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct drm_device *dev = nv_crtc->base.dev; nv_crtc 770 drivers/gpu/drm/nouveau/dispnv04/crtc.c rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; nv_crtc 781 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); nv_crtc 788 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 789 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (disp->image[nv_crtc->index]) nv_crtc 790 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(disp->image[nv_crtc->index]); nv_crtc 791 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); nv_crtc 799 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 806 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (!nv_crtc->base.primary->fb) { nv_crtc 807 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->lut.depth = 0; nv_crtc 821 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 824 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 829 drivers/gpu/drm/nouveau/dispnv04/crtc.c NV_DEBUG(drm, "index %d\n", nv_crtc->index); nv_crtc 848 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->fb.offset = fb->nvbo->bo.offset; nv_crtc 850 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (nv_crtc->lut.depth != drm_fb->format->depth) { nv_crtc 851 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->lut.depth = drm_fb->format->depth; nv_crtc 862 drivers/gpu/drm/nouveau/dispnv04/crtc.c NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, nv_crtc 875 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->fb_start = nv_crtc->fb.offset & ~3; nv_crtc 877 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); nv_crtc 988 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 994 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->cursor.hide(nv_crtc, true); nv_crtc 1011 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); nv_crtc 1013 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); nv_crtc 1016 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; nv_crtc 1017 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); nv_crtc 1018 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->cursor.show(nv_crtc, true); nv_crtc 1027 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 1029 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->cursor.set_pos(nv_crtc, x, y); nv_crtc 1298 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nouveau_crtc *nv_crtc; nv_crtc 1301 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); nv_crtc 1302 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (!nv_crtc) nv_crtc 1305 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->lut.depth = 0; nv_crtc 1307 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->index = crtc_num; nv_crtc 1308 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->last_dpms = NV_DPMS_CLEARED; nv_crtc 1310 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->save = nv_crtc_save; nv_crtc 1311 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv_crtc->restore = nv_crtc_restore; nv_crtc 1313 drivers/gpu/drm/nouveau/dispnv04/crtc.c drm_crtc_init_with_planes(dev, &nv_crtc->base, nv_crtc 1316 drivers/gpu/drm/nouveau/dispnv04/crtc.c drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); nv_crtc 1317 drivers/gpu/drm/nouveau/dispnv04/crtc.c drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); nv_crtc 1321 drivers/gpu/drm/nouveau/dispnv04/crtc.c &nv_crtc->cursor.nvbo); nv_crtc 1323 drivers/gpu/drm/nouveau/dispnv04/crtc.c ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); nv_crtc 1325 drivers/gpu/drm/nouveau/dispnv04/crtc.c ret = nouveau_bo_map(nv_crtc->cursor.nvbo); nv_crtc 1327 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_unpin(nv_crtc->cursor.nvbo); nv_crtc 1330 drivers/gpu/drm/nouveau/dispnv04/crtc.c nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); nv_crtc 1333 drivers/gpu/drm/nouveau/dispnv04/crtc.c nv04_cursor_init(nv_crtc); nv_crtc 9 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) nv_crtc 11 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); nv_crtc 15 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) nv_crtc 17 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); nv_crtc 21 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) nv_crtc 23 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; nv_crtc 24 drivers/gpu/drm/nouveau/dispnv04/cursor.c NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, nv_crtc 38 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) nv_crtc 40 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct drm_device *dev = nv_crtc->base.dev; nv_crtc 42 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 43 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct drm_crtc *crtc = &nv_crtc->base; nv_crtc 59 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv_fix_nv40_hw_cursor(dev, nv_crtc->index); nv_crtc 415 drivers/gpu/drm/nouveau/dispnv04/dac.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 422 drivers/gpu/drm/nouveau/dispnv04/dac.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); nv_crtc 117 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_crtc *nv_crtc; nv_crtc 121 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 122 drivers/gpu/drm/nouveau/dispnv04/dfp.c fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; nv_crtc 129 drivers/gpu/drm/nouveau/dispnv04/dfp.c *fpc = nv_crtc->dpms_saved_fp_control; nv_crtc 132 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index; nv_crtc 133 drivers/gpu/drm/nouveau/dispnv04/dfp.c NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc); nv_crtc 136 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_crtc = nouveau_crtc(crtc); nv_crtc 137 drivers/gpu/drm/nouveau/dispnv04/dfp.c fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; nv_crtc 139 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index); nv_crtc 140 drivers/gpu/drm/nouveau/dispnv04/dfp.c if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) { nv_crtc 141 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_crtc->dpms_saved_fp_control = *fpc; nv_crtc 145 drivers/gpu/drm/nouveau/dispnv04/dfp.c NVWriteRAMDAC(dev, nv_crtc->index, nv_crtc 286 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 287 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 288 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; nv_crtc 289 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc); nv_crtc 296 drivers/gpu/drm/nouveau/dispnv04/dfp.c NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index); nv_crtc 450 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 482 drivers/gpu/drm/nouveau/dispnv04/dfp.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); nv_crtc 65 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 66 drivers/gpu/drm/nouveau/dispnv04/disp.c if (nv_crtc->cursor.nvbo) { nv_crtc 67 drivers/gpu/drm/nouveau/dispnv04/disp.c if (nv_crtc->cursor.set_offset) nv_crtc 68 drivers/gpu/drm/nouveau/dispnv04/disp.c nouveau_bo_unmap(nv_crtc->cursor.nvbo); nv_crtc 69 drivers/gpu/drm/nouveau/dispnv04/disp.c nouveau_bo_unpin(nv_crtc->cursor.nvbo); nv_crtc 92 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 93 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->save(&nv_crtc->base); nv_crtc 119 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 120 drivers/gpu/drm/nouveau/dispnv04/disp.c if (!nv_crtc->cursor.nvbo) nv_crtc 123 drivers/gpu/drm/nouveau/dispnv04/disp.c ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, true); nv_crtc 124 drivers/gpu/drm/nouveau/dispnv04/disp.c if (!ret && nv_crtc->cursor.set_offset) nv_crtc 125 drivers/gpu/drm/nouveau/dispnv04/disp.c ret = nouveau_bo_map(nv_crtc->cursor.nvbo); nv_crtc 132 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 134 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->lut.depth = 0; nv_crtc 148 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 150 drivers/gpu/drm/nouveau/dispnv04/disp.c if (!nv_crtc->cursor.nvbo) nv_crtc 153 drivers/gpu/drm/nouveau/dispnv04/disp.c if (nv_crtc->cursor.set_offset) nv_crtc 154 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); nv_crtc 155 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x, nv_crtc 156 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->cursor_saved_y); nv_crtc 168 drivers/gpu/drm/nouveau/dispnv04/disp.c struct nouveau_crtc *nv_crtc; nv_crtc 174 drivers/gpu/drm/nouveau/dispnv04/disp.c list_for_each_entry(nv_crtc, &dev->mode_config.crtc_list, base.head) nv_crtc 175 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->restore(&nv_crtc->base); nv_crtc 124 drivers/gpu/drm/nouveau/dispnv04/overlay.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 127 drivers/gpu/drm/nouveau/dispnv04/overlay.c int soff = NV_PCRTC0_SIZE * nv_crtc->index; nv_crtc 128 drivers/gpu/drm/nouveau/dispnv04/overlay.c int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index; nv_crtc 145 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 146 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; nv_crtc 169 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 176 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); nv_crtc 576 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 603 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); nv_crtc 390 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 391 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); nv_crtc 396 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); nv_crtc 483 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) nv_crtc 495 drivers/gpu/drm/nouveau/dispnv50/disp.c (0x0100 << nv_crtc->index), nv_crtc 505 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 519 drivers/gpu/drm/nouveau/dispnv50/disp.c (0x0100 << nv_crtc->index), nv_crtc 536 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) nv_crtc 548 drivers/gpu/drm/nouveau/dispnv50/disp.c (0x0100 << nv_crtc->index), nv_crtc 559 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 570 drivers/gpu/drm/nouveau/dispnv50/disp.c (0x0100 << nv_crtc->index), nv_crtc 1430 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); nv_crtc 1434 drivers/gpu/drm/nouveau/dispnv50/disp.c if (nv_crtc) { nv_crtc 1447 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); nv_crtc 1448 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_audio_disable(encoder, nv_crtc); nv_crtc 1449 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); nv_crtc 1458 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 1459 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); nv_crtc 1548 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); nv_crtc 1675 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); nv_crtc 1677 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); nv_crtc 1679 drivers/gpu/drm/nouveau/dispnv50/disp.c u8 owner = 1 << nv_crtc->index; nv_crtc 157 drivers/gpu/drm/nouveau/nouveau_connector.h nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc) nv_crtc 159 drivers/gpu/drm/nouveau/nouveau_connector.h struct drm_device *dev = nv_crtc->base.dev; nv_crtc 163 drivers/gpu/drm/nouveau/nouveau_connector.h struct drm_crtc *crtc = to_drm_crtc(nv_crtc); nv_crtc 50 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_crtc *nv_crtc = nv_crtc 51 drivers/gpu/drm/nouveau/nouveau_display.c container_of(notify, typeof(*nv_crtc), vblank); nv_crtc 52 drivers/gpu/drm/nouveau/nouveau_display.c drm_crtc_handle_vblank(&nv_crtc->base); nv_crtc 60 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_crtc *nv_crtc; nv_crtc 66 drivers/gpu/drm/nouveau/nouveau_display.c nv_crtc = nouveau_crtc(crtc); nv_crtc 67 drivers/gpu/drm/nouveau/nouveau_display.c nvif_notify_get(&nv_crtc->vblank); nv_crtc 76 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_crtc *nv_crtc; nv_crtc 82 drivers/gpu/drm/nouveau/nouveau_display.c nv_crtc = nouveau_crtc(crtc); nv_crtc 83 drivers/gpu/drm/nouveau/nouveau_display.c nvif_notify_put(&nv_crtc->vblank); nv_crtc 162 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 163 drivers/gpu/drm/nouveau/nouveau_display.c nvif_notify_fini(&nv_crtc->vblank); nv_crtc 175 drivers/gpu/drm/nouveau/nouveau_display.c struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc 180 drivers/gpu/drm/nouveau/nouveau_display.c .head = nv_crtc->index, nv_crtc 184 drivers/gpu/drm/nouveau/nouveau_display.c &nv_crtc->vblank);